testsuite/synth: add a test for #1241

3 files changed, 72 insertions, 0 deletions

diff --git a/testsuite/synth/issue1241/tb_top.vhdl b/testsuite/synth/issue1241/tb_top.vhdl
new file mode 100644
index 000000000..653420122
--- /dev/null
+++ b/testsuite/synth/issue1241/tb_top.vhdl
@@ -0,0 +1,37 @@
+entity tb_top is
+end tb_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_top is
+  signal sel : unsigned(1 downto 0);
+  signal data : std_logic_vector(3 downto 0);
+  signal q : std_logic;
+begin
+  dut: entity work.top
+    port map (sel, data, q);
+
+  process
+  begin
+    data <= "1001";
+    sel <= "10";
+    wait for 1 ns;
+    assert q = '0' severity failure;
+
+    sel <= "11";
+    wait for 1 ns;
+    assert q = '1' severity failure;
+
+    sel <= "00";
+    wait for 1 ns;
+    assert q = '1' severity failure;
+
+    sel <= "01";
+    wait for 1 ns;
+    assert q = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1241/testsuite.sh b/testsuite/synth/issue1241/testsuite.sh
new file mode 100755
index 000000000..60399a753
--- /dev/null
+++ b/testsuite/synth/issue1241/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb top
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1241/top.vhdl b/testsuite/synth/issue1241/top.vhdl
new file mode 100644
index 000000000..c45aff954
--- /dev/null
+++ b/testsuite/synth/issue1241/top.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity top is
+	port(
+		sel : in unsigned(1 downto 0);
+		data : in std_logic_vector(3 downto 0);
+		q : out std_logic
+	);
+end entity;
+
+architecture arch of top is
+	type record_t is record
+		x : std_logic_vector(1 downto 0);
+		y : std_logic_vector(1 downto 0);
+	end record;
+
+	type array_t is array (0 to 1) of record_t;
+	signal a : array_t;
+begin
+	a <= (("11", data(1 downto 0)), ("11", data(3 downto 2)));
+	q <= a(to_integer(sel(1 downto 1))).y(to_integer(sel(0 downto 0)));
+end architecture;
+
+--  A0             A1
+--    Y1 Y0 X1 X0      Y1 Y0 X1 X0
+--  A + sel1*4 + 2 + sel0*1