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authorTristan Gingold <tgingold@free.fr>2020-03-13 19:20:43 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-13 19:20:43 +0100
commita13ef8cc10b50432300f2d376bcfa8fff24351b7 (patch)
treeccaa0fe5a8a526333f2234a75206a7fd1d8d1466
parent2143539b0943bc0917cb485c4571b8f9efe9df7f (diff)
downloadghdl-a13ef8cc10b50432300f2d376bcfa8fff24351b7.tar.gz
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vhdl: recognize more std_logic_arith operations.
-rw-r--r--python/libghdl/thin/vhdl/nodes.py32
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_arith.adb139
-rw-r--r--src/vhdl/vhdl-nodes.ads38
3 files changed, 207 insertions, 2 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 2da9debfd..82baa62c8 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1409,6 +1409,38 @@ class Iir_Predefined:
Ieee_Std_Logic_Arith_Conv_Vector_Uns = 426
Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 427
Ieee_Std_Logic_Arith_Conv_Vector_Log = 428
+ Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 429
+ Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 430
+ Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 431
+ Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 432
+ Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 433
+ Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 434
+ Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 435
+ Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 436
+ Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 437
+ Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 438
+ Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 439
+ Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 440
+ Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 441
+ Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 442
+ Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 443
+ Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 444
+ Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 445
+ Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 446
+ Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 447
+ Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 448
+ Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 449
+ Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 450
+ Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 451
+ Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 452
+ Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 453
+ Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 454
+ Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 455
+ Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 456
+ Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 457
+ Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 458
+ Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 459
+ Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 460
Get_Kind = libghdl.vhdl__nodes__get_kind
Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb
index e8a7fbd1b..352205585 100644
--- a/src/vhdl/vhdl-ieee-std_logic_arith.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb
@@ -27,12 +27,18 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Unsigned_Type : Iir := Null_Iir;
Signed_Type : Iir := Null_Iir;
- type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, Type_Log, Type_Slv);
+ type Arg_Kind is (Type_Slv, Type_Signed, Type_Unsigned, Type_Int, Type_Log);
subtype Conv_Arg_Kind is Arg_Kind range Type_Signed .. Type_Log;
type Conv_Pattern_Type is
array (Conv_Arg_Kind) of Iir_Predefined_Functions;
+ subtype Res_Arg_Kind is Arg_Kind range Type_Slv .. Type_Unsigned;
+
+ type Bin_Pattern_Type is
+ array (Res_Arg_Kind, Conv_Arg_Kind, Conv_Arg_Kind)
+ of Iir_Predefined_Functions;
+
Conv_Uns_Patterns : constant Conv_Pattern_Type :=
(Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns,
@@ -51,6 +57,124 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log);
+ Mul_Patterns : constant Bin_Pattern_Type :=
+ (Type_Slv =>
+ (Type_Unsigned =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv,
+ others => Iir_Predefined_None),
+ Type_Signed =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)),
+ Type_Signed =>
+ (Type_Signed =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn,
+ Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn,
+ others => Iir_Predefined_None),
+ Type_Unsigned =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)),
+ Type_Unsigned =>
+ (Type_Unsigned =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)));
+
+ Add_Patterns : constant Bin_Pattern_Type :=
+ (Type_Slv =>
+ (Type_Unsigned =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv,
+ Type_Int =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv,
+ Type_Log =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv,
+ others => Iir_Predefined_None),
+ Type_Signed =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv,
+ Type_Int =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv,
+ Type_Log =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv,
+ others => Iir_Predefined_None),
+ Type_Int =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv,
+ others => Iir_Predefined_None),
+ Type_Log =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Slv,
+ Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)),
+ Type_Signed =>
+ (Type_Signed =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn,
+ Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn,
+ Type_Int =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn,
+ Type_Log =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn,
+ others => Iir_Predefined_None),
+ Type_Unsigned =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn,
+ others => Iir_Predefined_None),
+ Type_Int =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn,
+ others => Iir_Predefined_None),
+ Type_Log =>
+ (Type_Signed =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)),
+ Type_Unsigned =>
+ (Type_Unsigned =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns,
+ Type_Int =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Uns,
+ Type_Log =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns,
+ others => Iir_Predefined_None),
+ Type_Int =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Uns,
+ others => Iir_Predefined_None),
+ Type_Log =>
+ (Type_Unsigned =>
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Uns,
+ others => Iir_Predefined_None),
+ others =>
+ (others => Iir_Predefined_None)));
+
Error : exception;
procedure Extract_Declarations (Pkg : Iir_Package_Declaration)
@@ -79,6 +203,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Arg1, Arg2 : Iir;
Arg1_Kind, Arg2_Kind : Arg_Kind;
+ Res_Kind : Arg_Kind;
function Handle_Conv (Pats : Conv_Pattern_Type)
return Iir_Predefined_Functions is
@@ -89,6 +214,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is
return Pats (Arg1_Kind);
end Handle_Conv;
+ function Handle_Bin (Pats : Bin_Pattern_Type)
+ return Iir_Predefined_Functions is
+ begin
+ return Pats (Res_Kind, Arg1_Kind, Arg2_Kind);
+ end Handle_Bin;
+
Def : Iir_Predefined_Functions;
begin
Decl := Get_Declaration_Chain (Pkg);
@@ -156,6 +287,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Classify_Arg (Arg2, Arg2_Kind);
case Get_Identifier (Decl) is
+ when Name_Op_Plus =>
+ Classify_Arg (Decl, Res_Kind);
+ Def := Handle_Bin (Add_Patterns);
+ when Name_Op_Mul =>
+ Classify_Arg (Decl, Res_Kind);
+ Def := Handle_Bin (Mul_Patterns);
when Name_Conv_Unsigned =>
Def := Handle_Conv (Conv_Uns_Patterns);
when Name_Conv_Std_Logic_Vector =>
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index ed83cd157..56c231301 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5751,7 +5751,43 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn,
- Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log
+ Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log,
+
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn,
+
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv,
+
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn,
+
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv
);
-- Return TRUE iff FUNC is a short-cut predefined function.