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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-31 07:39:21 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-31 07:39:21 +0200 |
| commit | a785e3f228a5370d2f6550d893213a501a368cd0 (patch) | |
| tree | 744c2ba79b454399c4b491016a9e051fe445bcc7 | |
| parent | eed73a6969ebdcac2aca1c03b6fc16b09af12fbd (diff) | |
| download | ghdl-a785e3f228a5370d2f6550d893213a501a368cd0.tar.gz ghdl-a785e3f228a5370d2f6550d893213a501a368cd0.tar.bz2 ghdl-a785e3f228a5370d2f6550d893213a501a368cd0.zip | |
testsuite/synth/issue1069: renaming.
| -rw-r--r-- | testsuite/synth/issue1069/ram3.vhdl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/testsuite/synth/issue1069/ram3.vhdl b/testsuite/synth/issue1069/ram3.vhdl index f63c11ae0..67f155bd3 100644 --- a/testsuite/synth/issue1069/ram3.vhdl +++ b/testsuite/synth/issue1069/ram3.vhdl @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; -entity tdp_ram is +entity ram3 is generic ( ADDRWIDTH : positive := 12; WIDTH : positive := 8 @@ -22,9 +22,9 @@ entity tdp_ram is data_read_b : out std_logic_vector(WIDTH - 1 downto 0); data_write_b : in std_logic_vector(WIDTH - 1 downto 0) ); -end tdp_ram; +end ram3; -architecture behavioral of tdp_ram is +architecture behavioral of ram3 is signal reg_a : std_logic_vector(WIDTH - 1 downto 0); signal reg_b : std_logic_vector(WIDTH - 1 downto 0); begin |