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| author | Tristan Gingold <tgingold@free.fr> | 2020-06-01 08:05:20 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-06-01 08:05:20 +0200 |
| commit | b5131047ec5988893c40428d8cb9823f4c914bc4 (patch) | |
| tree | 716ca821933edbe11ee71d3c248711a63e6aa91d | |
| parent | eaae9cb33f67aa6cf230e345724511b4b4d5c9cf (diff) | |
| download | ghdl-b5131047ec5988893c40428d8cb9823f4c914bc4.tar.gz ghdl-b5131047ec5988893c40428d8cb9823f4c914bc4.tar.bz2 ghdl-b5131047ec5988893c40428d8cb9823f4c914bc4.zip | |
testsuite/gna: add test from #1346
| -rw-r--r-- | testsuite/gna/issue1346/memory_map.vhd | 68 | ||||
| -rw-r--r-- | testsuite/gna/issue1346/memory_map_pkg.vhd | 34 | ||||
| -rwxr-xr-x | testsuite/gna/issue1346/testsuite.sh | 11 | ||||
| -rw-r--r-- | testsuite/gna/issue1346/wb_pkg.vhd | 66 | ||||
| -rw-r--r-- | testsuite/gna/issue1346/wb_rst_pkg.vhd | 109 |
5 files changed, 288 insertions, 0 deletions
diff --git a/testsuite/gna/issue1346/memory_map.vhd b/testsuite/gna/issue1346/memory_map.vhd new file mode 100644 index 000000000..f55dd64a1 --- /dev/null +++ b/testsuite/gna/issue1346/memory_map.vhd @@ -0,0 +1,68 @@ +library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use ieee.MATH_REAL.all;
+
+library work;
+ use work.wb_rst_pkg.all;
+ use work.memory_map_pkg.all;
+
+entity memory_map is
+ generic
+ ( yes_g : std_logic :='1'
+ );
+ port
+ ( p_i : in memory_map_i_t;
+ p_o : out memory_map_o_t
+ );
+
+end memory_map;
+architecture rtl of memory_map is
+
+ alias clk_i : std_ulogic is p_i.dmn.clk;
+ alias rst_i : std_ulogic is p_i.dmn.rst;
+
+ type reg_t is record
+ p_o
+ : memory_map_o_t
+ ( wb_S2M
+ ( tgd( 0 downto 0 )
+ , dat( p_i.wb_M2S.dat'length - 1 downto 0 ) )
+ , en( p_o.en'length - 1 downto 0 )
+ , reg( 0 to p_o.en'length - 1 )( p_o.dat'length - 1 downto 0 )
+ );
+
+ end record;
+
+ signal a
+ , r
+ : reg_t;
+
+begin
+
+ p_o <= r.p_o;
+
+ process( p_i, r )
+ variable a_v : reg_t;
+ begin
+ a_v := r;
+
+ if rst_i = yes_g then
+ set_wb_rst( a_v.p_o.wb_S2M );
+ end if;
+
+ a <= a_v;
+ end process;
+
+ process( clk_i )
+ begin
+ if rising_edge ( clk_i ) then
+ r <= a;
+ end if;
+ end process;
+end rtl;
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
diff --git a/testsuite/gna/issue1346/memory_map_pkg.vhd b/testsuite/gna/issue1346/memory_map_pkg.vhd new file mode 100644 index 000000000..1dc2b7e87 --- /dev/null +++ b/testsuite/gna/issue1346/memory_map_pkg.vhd @@ -0,0 +1,34 @@ +
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.wb_pkg.all;
+
+package memory_map_pkg is
+
+ type memory_map_i_t is record
+ dmn : dmn_t;
+ wb_M2S : wb_M2S_t;
+ reg : array_t;
+ end record;
+
+ type memory_map_o_t is record
+ wb_S2M : wb_S2M_t;
+ en : std_ulogic_vector;
+ reg : array_t;
+ end record;
+
+end memory_map_pkg;
+--#############################################################################
+--=============================================================================
+--#############################################################################
+package body memory_map_pkg is
+
+end package body memory_map_pkg;
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
+--#######################################################################################
diff --git a/testsuite/gna/issue1346/testsuite.sh b/testsuite/gna/issue1346/testsuite.sh new file mode 100755 index 000000000..18800a4e5 --- /dev/null +++ b/testsuite/gna/issue1346/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 + +analyze_failure wb_pkg.vhd wb_rst_pkg.vhd memory_map_pkg.vhd memory_map.vhd + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue1346/wb_pkg.vhd b/testsuite/gna/issue1346/wb_pkg.vhd new file mode 100644 index 000000000..7779485b0 --- /dev/null +++ b/testsuite/gna/issue1346/wb_pkg.vhd @@ -0,0 +1,66 @@ +library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use ieee.math_real.all;
+
+package wb_pkg is
+
+ constant wb_no_c : std_ulogic := '0';
+
+ type array_t is array (integer range <> ) of std_ulogic_vector;
+
+ type dmn_t is record
+ clk : std_ulogic;
+ rst : std_ulogic;
+ end record;
+
+ --! WISHBONE master to slave signals type
+ type wb_M2S_t is record
+ tgc : std_ulogic_vector ; --! cycle tag
+ loc : std_ulogic ; --! lock
+ cyc : std_ulogic ; --! cycle
+ stb : std_ulogic ; --! strobe
+ we : std_ulogic ; --! write transaction
+ tga : std_ulogic_vector ; --! Address tag
+ adr : std_ulogic_vector ; --! address
+ bte : std_ulogic_vector(1 downto 0); --! burst type extension
+ sel : std_ulogic_vector ; --! Byte selection
+ tgd : std_ulogic_vector ; --! data tag master to slave
+ dat : std_ulogic_vector ; --! data master to slave
+ end record;
+
+ --! WISHBONE slave to master signals type
+ type wb_S2M_t is record
+ stl : std_ulogic ; --! stall pipeline
+ tgd : std_ulogic_vector; --! data tag slave to master
+ dat : std_ulogic_vector; --! data slave to master
+ ack : std_ulogic ; --! acknowledgement slave to master
+ err : std_ulogic ; --! error slave to master
+ rty : std_ulogic ; --! retry slave to master
+ end record;
+
+ pure function get_uvect( len : positive ; bit_i : in std_ulogic := '0' )
+ return std_ulogic_vector;
+
+end wb_pkg;
+--#############################################################################
+--#############################################################################
+package body wb_pkg is
+
+ pure function get_uvect( len : positive ; bit_i : in std_ulogic := '0' )
+ return std_ulogic_vector
+ is
+ variable vect_v : std_ulogic_vector( len - 1 downto 0 );
+ begin
+ for i in 0 to len - 1 loop
+ vect_v( i ) := bit_i ;
+ end loop;
+ return vect_v;
+ end function;
+
+end package body wb_pkg;
+--#############################################################################
+--#############################################################################
+--#############################################################################
+--#############################################################################
+--#############################################################################
diff --git a/testsuite/gna/issue1346/wb_rst_pkg.vhd b/testsuite/gna/issue1346/wb_rst_pkg.vhd new file mode 100644 index 000000000..499841a05 --- /dev/null +++ b/testsuite/gna/issue1346/wb_rst_pkg.vhd @@ -0,0 +1,109 @@ +library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.wb_pkg.all;
+
+package wb_rst_pkg is
+
+ pure function get_wb_rst( wb_i : wb_M2S_t)
+ return wb_M2S_t;
+
+ pure function get_wb_rst( wb_i : wb_S2M_t)
+ return wb_S2M_t;
+
+ procedure set_wb_rst( wb_o : out wb_M2S_t);
+ procedure set_wb_rst( wb_o : out wb_S2M_t);
+
+end wb_rst_pkg;
+--#############################################################################
+--#############################################################################
+package body wb_rst_pkg is
+
+ pure function get_wb_rst( wb_i : wb_M2S_t)
+ return wb_M2S_t
+ is
+ variable wb_v
+ : wb_M2S_t
+ ( tgc( wb_i.tgc'length - 1 downto 0)
+ , tga( wb_i.tga'length - 1 downto 0)
+ , adr( wb_i.adr'length - 1 downto 0)
+ , sel( wb_i.sel'length - 1 downto 0)
+ , tgd( wb_i.tgd'length - 1 downto 0)
+ , dat( wb_i.dat'length - 1 downto 0)
+ );
+
+ begin
+
+ wb_v.tgc := get_uvect( wb_i.tgc'length, 'X' );
+ wb_v.loc := wb_no_c;
+ wb_v.cyc := wb_no_c;
+ wb_v.stb := wb_no_c;
+ wb_v.we := 'X';
+ wb_v.tga := get_uvect( wb_i.tga'length, 'X' );
+ wb_v.adr := get_uvect( wb_i.adr'length, 'X' );
+ wb_v.bte := get_uvect( wb_i.bte'length, 'X' );
+ wb_v.sel := get_uvect( wb_i.sel'length, 'X' );
+ wb_v.tgd := get_uvect( wb_i.tgd'length, 'X' );
+ wb_v.dat := get_uvect( wb_i.dat'length, 'X' );
+
+ return wb_v;
+ end function;
+
+ pure function get_wb_rst( wb_i : wb_S2M_t)
+ return wb_S2M_t
+ is
+ variable wb_v
+ : wb_S2M_t
+ ( tgd( wb_i.tgd'length - 1 downto 0)
+ , dat( wb_i.dat'length - 1 downto 0)
+ );
+
+ begin
+
+ wb_v.tgd := get_uvect( wb_i.tgd'length, 'X' );
+ wb_v.dat := get_uvect( wb_i.dat'length, 'X' );
+ wb_v.stl := wb_no_c;
+ wb_v.ack := wb_no_c;
+ wb_v.err := wb_no_c;
+ wb_v.rty := wb_no_c;
+
+ return wb_v;
+ end function;
+
+ procedure set_wb_rst( wb_o : out wb_M2S_t)
+ is
+ variable wb_v
+ : wb_M2S_t
+ ( tgc( wb_o.tgc'length - 1 downto 0)
+ , tga( wb_o.tga'length - 1 downto 0)
+ , adr( wb_o.adr'length - 1 downto 0)
+ , sel( wb_o.sel'length - 1 downto 0)
+ , tgd( wb_o.tgd'length - 1 downto 0)
+ , dat( wb_o.dat'length - 1 downto 0)
+ );
+
+ begin
+ wb_v := get_wb_rst( wb_v );
+ wb_o := wb_v;
+ end procedure;
+
+ procedure set_wb_rst( wb_o : out wb_S2M_t)
+ is
+ variable wb_v
+ : wb_S2M_t
+ ( tgd( wb_o.tgd'length - 1 downto 0)
+ , dat( wb_o.dat'length - 1 downto 0)
+ );
+ begin
+ wb_v := get_wb_rst( wb_v );
+ wb_o := wb_v;
+ end procedure;
+
+end package body wb_rst_pkg;
+--#############################################################################
+--#############################################################################
+--#############################################################################
+--#############################################################################
+--#############################################################################
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