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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-16 12:13:54 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-16 12:13:54 +0200 |
| commit | bd29c849be41a8d15a6f6231a7664e8a7841a1b2 (patch) | |
| tree | ba07c740df5df11f327da6df132adeea540d1574 | |
| parent | fb72fae0a907684c00bb19950ad9a20c21732f77 (diff) | |
| download | ghdl-bd29c849be41a8d15a6f6231a7664e8a7841a1b2.tar.gz ghdl-bd29c849be41a8d15a6f6231a7664e8a7841a1b2.tar.bz2 ghdl-bd29c849be41a8d15a6f6231a7664e8a7841a1b2.zip | |
synth: handle integers for displaying vhdl ports.
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 2abd0da44..351febe8b 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -143,6 +143,16 @@ package body Synth.Disp_Vhdl is New_Line; Idx := Idx + 1; end if; + when Iir_Kind_Integer_Type_Definition => + -- FIXME: signed or unsigned ? + Put (" " & Pfx & " <= to_integer (unsigned"); + if Desc.W = 1 then + Put ("'(0 => wrap_" & Pfx & ')'); + else + Put (" (wrap_" & Pfx & ')'); + end if; + Put_Line (");"); + Idx := Idx + 1; when Iir_Kind_Array_Type_Definition => if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then -- Nothing to do. |