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author | Tristan Gingold <tgingold@free.fr> | 2020-02-23 08:45:26 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-23 08:45:26 +0100 |
commit | c6e5cfd09db4bb1c6d1d8de21ccff5007c7f452d (patch) | |
tree | 722c6e8dffb47478987b96e260fb88c722d4b948 | |
parent | c121783be11334acd9226ef3962f5595c72e59d8 (diff) | |
download | ghdl-c6e5cfd09db4bb1c6d1d8de21ccff5007c7f452d.tar.gz ghdl-c6e5cfd09db4bb1c6d1d8de21ccff5007c7f452d.tar.bz2 ghdl-c6e5cfd09db4bb1c6d1d8de21ccff5007c7f452d.zip |
testsuites/synth: add missing files.
-rw-r--r-- | testsuite/synth/mem01/tb_sram02.vhdl | 47 | ||||
-rw-r--r-- | testsuite/synth/mem01/tb_sram03.vhdl | 50 |
2 files changed, 97 insertions, 0 deletions
diff --git a/testsuite/synth/mem01/tb_sram02.vhdl b/testsuite/synth/mem01/tb_sram02.vhdl new file mode 100644 index 000000000..2862f7400 --- /dev/null +++ b/testsuite/synth/mem01/tb_sram02.vhdl @@ -0,0 +1,47 @@ +entity tb_sram02 is +end tb_sram02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_sram02 is + signal addr : std_logic_vector(3 downto 0); + signal rdat : std_logic_vector(7 downto 0); + signal wdat : std_logic_vector(7 downto 0); + signal wen : std_logic; + signal clk : std_logic; +begin + dut: entity work.sram02 + port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat, + wen_i => wen); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + addr <= "0000"; + wdat <= x"02"; + wen <= '1'; + pulse; + assert rdat = x"02" severity failure; + + addr <= "0100"; + wdat <= x"03"; + wait for 1 ns; + assert rdat = x"02" severity failure; + pulse; + assert rdat = x"03" severity failure; + + addr <= "0000"; + wen <= '0'; + pulse; + assert rdat = x"02" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/mem01/tb_sram03.vhdl b/testsuite/synth/mem01/tb_sram03.vhdl new file mode 100644 index 000000000..96cc80975 --- /dev/null +++ b/testsuite/synth/mem01/tb_sram03.vhdl @@ -0,0 +1,50 @@ +entity tb_sram03 is +end tb_sram03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_sram03 is + signal addr : std_logic_vector(3 downto 0); + signal rdat : std_logic_vector(7 downto 0); + signal wdat : std_logic_vector(7 downto 0); + signal wen : std_logic; + signal clk : std_logic; +begin + dut: entity work.sram03 + port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat, + wen_i => wen); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + addr <= "0000"; + wdat <= x"03"; + wen <= '1'; + pulse; + + wdat <= x"41"; + pulse; + assert rdat = x"03" severity failure; + + addr <= "0100"; + wdat <= x"07"; + wait for 1 ns; + pulse; + pulse; + assert rdat = x"07" severity failure; + + addr <= "0000"; + wen <= '0'; + pulse; + assert rdat = x"41" severity failure; + + wait; + end process; +end behav; |