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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:30:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-10 18:30:30 +0200 |
| commit | cea222fe918c82de7b8ce75f3bd42c011677e06d (patch) | |
| tree | 7d68698d7e1838647f519286d8d8b5d88bec087b | |
| parent | 6b3077ca2b4eac97d176f84f90e4e237315454a6 (diff) | |
| download | ghdl-cea222fe918c82de7b8ce75f3bd42c011677e06d.tar.gz ghdl-cea222fe918c82de7b8ce75f3bd42c011677e06d.tar.bz2 ghdl-cea222fe918c82de7b8ce75f3bd42c011677e06d.zip | |
synth: handle constants for enum equality.
| -rw-r--r-- | src/synth/synth-oper.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 353cd95e1..5828ce0f2 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -439,8 +439,12 @@ package body Synth.Oper is return Synth_Vec_Dyadic (Id_Xnor); when Iir_Predefined_Enum_Equality => + if Is_Const (Left) and then Is_Const (Right) then + return Create_Value_Discrete + (Boolean'Pos (Left.Scal = Right.Scal), Boolean_Type); + end if; if Left_Typ.Kind = Type_Bit then - pragma Assert (Is_Bit_Type (Right_Type)); + pragma Assert (Right.Typ.Kind = Type_Bit); if Is_Const (Left) then return Synth_Bit_Eq_Const (Left, Right, Expr); elsif Is_Const (Right) then |