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author | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:17:23 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:17:23 +0200 |
commit | d145f8b9f99463f310a466f2e8e114d1b61afaee (patch) | |
tree | cc53ea8b73878af0cc7b2d20a41dfb700a5a3c59 | |
parent | 336dbeaa305bdfe968a500161f561b35a9c495c0 (diff) | |
download | ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.tar.gz ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.tar.bz2 ghdl-d145f8b9f99463f310a466f2e8e114d1b61afaee.zip |
synth: introduce memidx1
-rw-r--r-- | src/synth/netlists-builders.adb | 14 | ||||
-rw-r--r-- | src/synth/netlists-builders.ads | 7 | ||||
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 15 | ||||
-rw-r--r-- | src/synth/netlists-gates.ads | 2 | ||||
-rw-r--r-- | src/synth/synth-expr.adb | 11 | ||||
-rw-r--r-- | src/synth/synth-expr.ads | 3 | ||||
-rw-r--r-- | src/synth/synth-stmts.adb | 11 |
7 files changed, 35 insertions, 28 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index 12aee039d..f27d82723 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -982,10 +982,10 @@ package body Netlists.Builders is end Build_Dyn_Insert; function Build_Memidx1 - (Ctxt : Context_Acc; I : Net; Step : Uns32; Max : Uns32) return Net + (Ctxt : Context_Acc; + I : Net; Step : Uns32; Max : Uns32; W : Width) return Net is - W : constant Width := Get_Width (I); - pragma Assert (W /= No_Width); + pragma Assert (Get_Width (I) /= No_Width); pragma Assert (Step > 0); pragma Assert (W > 0); Inst : Instance; @@ -1001,12 +1001,10 @@ package body Netlists.Builders is end Build_Memidx1; function Build_Memidx2 - (Ctxt : Context_Acc; I : Net; Add : Net; Step : Uns32; Max : Uns32) - return Net + (Ctxt : Context_Acc; + I : Net; Add : Net; Step : Uns32; Max : Uns32; W : Width) return Net is - W : constant Width := Get_Width (I); - pragma Assert (W /= No_Width); - pragma Assert (Get_Width (Add) = W); + pragma Assert (Get_Width (I) /= No_Width); pragma Assert (Get_Width (Add) /= No_Width); pragma Assert (Step > 0); pragma Assert (W > 0); diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads index a00014168..920395cf8 100644 --- a/src/synth/netlists-builders.ads +++ b/src/synth/netlists-builders.ads @@ -137,10 +137,11 @@ package Netlists.Builders is return Net; function Build_Memidx1 - (Ctxt : Context_Acc; I : Net; Step : Uns32; Max : Uns32) return Net; + (Ctxt : Context_Acc; + I : Net; Step : Uns32; Max : Uns32; W : Width) return Net; function Build_Memidx2 - (Ctxt : Context_Acc; I : Net; Add : Net; Step : Uns32; Max : Uns32) - return Net; + (Ctxt : Context_Acc; + I : Net; Add : Net; Step : Uns32; Max : Uns32; W : Width) return Net; function Build_Output (Ctxt : Context_Acc; W : Width) return Net; function Build_Signal (Ctxt : Context_Acc; Name : Sname; W : Width) diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index d83edfeec..fed799508 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -586,6 +586,21 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= ", Inst); Disp_Extract (Inst); Put_Line (";"); + when Id_Memidx1 => + declare + O : constant Net := Get_Output (Inst, 0); + Wd : constant Width := Get_Width (O); + Step : constant Uns32 := Get_Param_Uns32 (Inst, 0); + begin + if Step /= 1 then + Disp_Template + (" \o0 <= std_logic_vector " + & "(resize (resize (\ui0, \n0) * \up0, \n0));" + & NL, Inst, (0 => Wd)); + else + Disp_Template (" \o0 <= \i0;" & NL, Inst); + end if; + end; when Id_Dyn_Extract => declare O : constant Net := Get_Output (Inst, 0); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 41cb597f6..818a7eee2 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -156,7 +156,7 @@ package Netlists.Gates is -- OUT := IN0 * STEP, IN0 < MAX Id_Memidx1 : constant Module_Id := 71; - -- OUT := IN0 * STEP + IN1, IN0 < MAX + -- OUT := IN0 * STEP + IN1, IN0 < MAX, size extension. Id_Memidx2 : constant Module_Id := 72; -- Positive/rising edge detector. This is a pseudo gate. diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index f87f8d77b..308b84150 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -942,7 +942,6 @@ package body Synth.Expr is Name : Node; Pfx_Type : Type_Acc; Voff : out Net; - Mul : out Uns32; Off : out Uns32; W : out Width) is @@ -968,12 +967,12 @@ package body Synth.Expr is if Idx_Val.Kind = Value_Discrete then Voff := No_Net; - Mul := 0; Off := Index_To_Offset (Bnd, Idx_Val.Scal, Name) * W; else Voff := Dyn_Index_To_Offset (Bnd, Idx_Val, Name); + Voff := Build_Memidx1 (Get_Build (Syn_Inst), Voff, W, Bnd.Len, + Width (Clog2 (Uns64 (W * Bnd.Len)))); Off := 0; - Mul := W; end if; end Synth_Indexed_Name; @@ -982,7 +981,6 @@ package body Synth.Expr is is Pfx_Val : Value_Acc; Voff : Net; - Mul : Uns32; Off : Uns32; W : Width; El_Typ : Type_Acc; @@ -990,11 +988,10 @@ package body Synth.Expr is begin Pfx_Val := Synth_Expression (Syn_Inst, Get_Prefix (Name)); - Synth_Indexed_Name (Syn_Inst, Name, Pfx_Val.Typ, Voff, Mul, Off, W); + Synth_Indexed_Name (Syn_Inst, Name, Pfx_Val.Typ, Voff, Off, W); El_Typ := Get_Array_Element (Pfx_Val.Typ); if Voff = No_Net then - pragma Assert (Mul = 0); if W = 1 and then Pfx_Val.Kind = Value_Array then return Bit_Extract (Pfx_Val, Off, Name); else @@ -1005,7 +1002,7 @@ package body Synth.Expr is else pragma Assert (Off = 0); Res := Build_Dyn_Extract (Build_Context, Get_Net (Pfx_Val), - Voff, Mul, Off, W); + Voff, 1, Off, W); Set_Location (Res, Name); return Create_Value_Net (Res, El_Typ); end if; diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index 92104fc75..d40e41eb3 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -104,11 +104,12 @@ package Synth.Expr is Off : out Uns32; Wd : out Uns32); + -- If VOFF is No_Net then OFF is valid, if VOFF is not No_Net then + -- OFF is 0. procedure Synth_Indexed_Name (Syn_Inst : Synth_Instance_Acc; Name : Node; Pfx_Type : Type_Acc; Voff : out Net; - Mul : out Uns32; Off : out Uns32; W : out Width); end Synth.Expr; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index e63c41d99..733607af2 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -148,21 +148,18 @@ package body Synth.Stmts is when Iir_Kind_Indexed_Name => declare Voff : Net; - Mul : Uns32; Off : Uns32; W : Width; begin Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Pfx), Dest_Obj, Dest_Off, Dest_Type); - Synth_Indexed_Name - (Syn_Inst, Pfx, Dest_Type, Voff, Mul, Off, W); + Synth_Indexed_Name (Syn_Inst, Pfx, Dest_Type, Voff, Off, W); if Voff /= No_Net then Error_Msg_Synth (+Pfx, "dynamic index must be the last suffix"); else -- FIXME: check index. - pragma Assert (Mul = 0); null; end if; @@ -281,7 +278,6 @@ package body Synth.Stmts is El_Typ : Type_Acc; Voff : Net; - Mul : Uns32; Idx_Off : Uns32; W : Width; @@ -291,12 +287,11 @@ package body Synth.Stmts is Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Target), Obj, Off, Typ); Synth_Indexed_Name (Syn_Inst, Target, Typ, - Voff, Mul, Idx_Off, W); + Voff, Idx_Off, W); El_Typ := Get_Array_Element (Typ); if Voff = No_Net then -- FIXME: check index. - pragma Assert (Mul = 0); return Target_Info'(Kind => Target_Simple, Targ_Type => El_Typ, Obj => Obj, @@ -305,7 +300,7 @@ package body Synth.Stmts is Targ_Net := Get_Current_Assign_Value (Build_Context, Obj.W, Off, Get_Type_Width (Typ)); V := Build_Dyn_Insert - (Build_Context, Targ_Net, No_Net, Voff, Mul, Idx_Off); + (Build_Context, Targ_Net, No_Net, Voff, 1, Idx_Off); Set_Location (V, Target); return Target_Info'(Kind => Target_Memory, Targ_Type => El_Typ, |