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| author | Tristan Gingold <tgingold@free.fr> | 2020-12-03 03:41:18 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-12-03 07:40:56 +0100 |
| commit | d253da38ff3f41e6940d9fb296bc32113d1b3f98 (patch) | |
| tree | 4bd5a08a88a2b909215f60d05c4cf22df6599163 | |
| parent | ad74ac7886532dd1a846712c92266158c8947589 (diff) | |
| download | ghdl-d253da38ff3f41e6940d9fb296bc32113d1b3f98.tar.gz ghdl-d253da38ff3f41e6940d9fb296bc32113d1b3f98.tar.bz2 ghdl-d253da38ff3f41e6940d9fb296bc32113d1b3f98.zip | |
synth: handle dyadic logical vec/log operations. Fix #1520
| -rw-r--r-- | src/synth/synth-oper.adb | 54 |
1 files changed, 52 insertions, 2 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index a3f7be688..4493db681 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -401,6 +401,29 @@ package body Synth.Oper is return Create_Value_Net (N, Create_Res_Bound (Right)); end Synth_Dyadic_Int_Sgn; + function Synth_Dyadic_Vec_Log (Ctxt : Context_Acc; + Id : Dyadic_Module_Id; + Vec, Log : Valtyp; + Expr : Node) return Valtyp + is + V : constant Net := Get_Net (Ctxt, Vec); + L : constant Net := Get_Net (Ctxt, Log); + Wd : constant Width := Get_Width (V); + Res : Net; + N : Net; + Inst : Instance; + begin + Res := Build_Concatn (Ctxt, Wd, Wd); + Inst := Get_Net_Parent (Res); + for I in 1 .. Wd loop + N := Build2_Extract (Ctxt, V, I - 1, 1); + N := Build_Dyadic (Ctxt, Id, N, L); + Set_Location (N, Expr); + Connect (Get_Input (Inst, Port_Nbr (Wd - I)), N); + end loop; + return Create_Value_Net (Res, Create_Res_Bound (Vec)); + end Synth_Dyadic_Vec_Log; + function Synth_Compare_Xxx_Xxx (Ctxt : Context_Acc; Id : Compare_Module_Id; W : Width; @@ -809,6 +832,31 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Xnor); + when Iir_Predefined_Ieee_1164_And_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_And, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_And_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_And, Right, Left, Expr); + when Iir_Predefined_Ieee_1164_Nand_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Nand, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_Nand_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Nand, Right, Left, Expr); + when Iir_Predefined_Ieee_1164_Or_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Or, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_Or_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Or, Right, Left, Expr); + when Iir_Predefined_Ieee_1164_Nor_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Nor, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_Nor_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Nor, Right, Left, Expr); + when Iir_Predefined_Ieee_1164_Xor_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Xor, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_Xor_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Xor, Right, Left, Expr); + when Iir_Predefined_Ieee_1164_Xnor_Suv_Log => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Xnor, Left, Right, Expr); + when Iir_Predefined_Ieee_1164_Xnor_Log_Suv => + return Synth_Dyadic_Vec_Log (Ctxt, Id_Xnor, Right, Left, Expr); + when Iir_Predefined_Enum_Equality => if Left_Typ = Bit_Type or else Left_Typ = Logic_Type @@ -1542,11 +1590,13 @@ package body Synth.Oper is return Synth_Shift (Id_Asr, Id_Lsl); when Iir_Predefined_Ieee_Numeric_Std_Sll_Uns_Int - | Iir_Predefined_Ieee_Numeric_Std_Sll_Sgn_Int => + | Iir_Predefined_Ieee_Numeric_Std_Sll_Sgn_Int + | Iir_Predefined_Ieee_1164_Vector_Sll => return Synth_Shift (Id_Lsl, Id_Lsr); when Iir_Predefined_Ieee_Numeric_Std_Srl_Uns_Int - | Iir_Predefined_Ieee_Numeric_Std_Srl_Sgn_Int => + | Iir_Predefined_Ieee_Numeric_Std_Srl_Sgn_Int + | Iir_Predefined_Ieee_1164_Vector_Srl => return Synth_Shift (Id_Lsr, Id_Lsl); when Iir_Predefined_Ieee_1164_Vector_Ror => |