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author | Tristan Gingold <tgingold@free.fr> | 2022-10-01 18:37:34 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-10-02 11:47:37 +0200 |
commit | da679767f9a25def8673bda1fe6cdc9e5047f990 (patch) | |
tree | 7f60470afa138f76688c4d0f60bc9309f3925633 | |
parent | 16c6edba870d326b9189e99d9937779c42d41e12 (diff) | |
download | ghdl-da679767f9a25def8673bda1fe6cdc9e5047f990.tar.gz ghdl-da679767f9a25def8673bda1fe6cdc9e5047f990.tar.bz2 ghdl-da679767f9a25def8673bda1fe6cdc9e5047f990.zip |
testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#174
-rw-r--r-- | testsuite/synth/synth174/repro.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/synth/synth174/testsuite.sh | 8 |
2 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/synth174/repro.vhdl b/testsuite/synth/synth174/repro.vhdl new file mode 100644 index 000000000..65783f51e --- /dev/null +++ b/testsuite/synth/synth174/repro.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is + generic (w : integer := 8); + port (a, b : std_logic_vector (w - 1 downto 0); + res : out std_logic_vector (w - 1 downto 0)); +end repro; + +architecture behav of repro is +begin + process + begin + report "w = " & natural'image(w); + if w <= 0 then + assert false + report "w value is <= 0" + severity error; + end if; + if w > 128 then + assert false + report "w value is large" + severity note; + end if; + wait; + end process; + + res <= a or b; +end behav; diff --git a/testsuite/synth/synth174/testsuite.sh b/testsuite/synth/synth174/testsuite.sh new file mode 100755 index 000000000..a066afad7 --- /dev/null +++ b/testsuite/synth/synth174/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only repro +synth_failure -gw=0 repro.vhdl -e + +echo "Test successful" |