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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-13 18:44:53 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-13 18:44:53 +0100 |
| commit | e73e219ec12f0a18d24940e8486ecf6a7ca7bec8 (patch) | |
| tree | 52eada884c36f096bb0c6120e5c34a311a1fe70b | |
| parent | 928762b7844d06e75a7dc5e86840969ba82b00fe (diff) | |
| download | ghdl-e73e219ec12f0a18d24940e8486ecf6a7ca7bec8.tar.gz ghdl-e73e219ec12f0a18d24940e8486ecf6a7ca7bec8.tar.bz2 ghdl-e73e219ec12f0a18d24940e8486ecf6a7ca7bec8.zip | |
synth: add support for static vector/vector or.
| -rw-r--r-- | src/synth/synth-ieee-std_logic_1164.ads | 15 | ||||
| -rw-r--r-- | src/synth/synth-static_oper.adb | 13 |
2 files changed, 22 insertions, 6 deletions
diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads index f54ef0257..c90e4e5ca 100644 --- a/src/synth/synth-ieee-std_logic_1164.ads +++ b/src/synth/synth-ieee-std_logic_1164.ads @@ -42,7 +42,7 @@ package Synth.Ieee.Std_Logic_1164 is type Table_2d is array (Std_Ulogic, Std_Ulogic) of Std_Ulogic; And_Table : constant Table_2d := - -- UX01ZWLH- + -- UX01ZWLH- ("UU0UUU0UU", -- U "UX0XXX0XX", -- X "000000000", -- 0 @@ -54,4 +54,17 @@ package Synth.Ieee.Std_Logic_1164 is "UX0XXX0XX" -- - ); + Or_Table : constant Table_2d := + -- UX01ZWLH- + ("UUU1UUU1U", -- U + "UXX1XXX1X", -- X + "UX01XX01X", -- 0 + "111111111", -- 1 + "UXX1XXX1X", -- Z + "UXX1XXX1X", -- W + "UX01XX01X", -- L + "111111111", -- H + "UXX1XXX1X" -- - + ); + end Synth.Ieee.Std_Logic_1164; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 9bf3ddb0d..e928d8fcb 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -41,8 +41,8 @@ package body Synth.Static_Oper is return Create_Vec_Type_By_Length (Prev.W, Prev.Vec_El); end Create_Res_Bound; - function Synth_Vector_And (L, R : Value_Acc; Loc : Syn_Src) - return Value_Acc + function Synth_Vector_Dyadic + (L, R : Value_Acc; Op : Table_2d; Loc : Syn_Src) return Value_Acc is El_Typ : constant Type_Acc := L.Typ.Vec_El; Arr : Value_Array_Acc; @@ -59,14 +59,14 @@ package body Synth.Static_Oper is Std_Ulogic'Val (L.Arr.V (I).Scal); Rs : constant Std_Ulogic := Std_Ulogic'Val (R.Arr.V (I).Scal); - V : constant Std_Ulogic := And_Table (Ls, Rs); + V : constant Std_Ulogic := Op (Ls, Rs); begin Arr.V (I) := Create_Value_Discrete (Std_Ulogic'Pos (V), El_Typ); end; end loop; return Create_Value_Const_Array (Create_Res_Bound (L.Typ), Arr); - end Synth_Vector_And; + end Synth_Vector_Dyadic; procedure To_Std_Logic_Vector (Val : Value_Acc; Arr : out Std_Logic_Vector) is @@ -187,7 +187,10 @@ package body Synth.Static_Oper is (Boolean'Pos (not Is_Equal (Left, Right)), Boolean_Type); when Iir_Predefined_Ieee_1164_Vector_And => - return Synth_Vector_And (Left, Right, Expr); + return Synth_Vector_Dyadic (Left, Right, And_Table, Expr); + + when Iir_Predefined_Ieee_1164_Vector_Or => + return Synth_Vector_Dyadic (Left, Right, Or_Table, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns => return Synth_Add_Uns_Uns (Left, Right, Expr); |