diff options
author | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:18:53 +0100 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:18:53 +0100 |
commit | e918d6e9030ac611ecd9c9c78b31c3c742c7cc13 (patch) | |
tree | 6be93fedffab752b31d3fad4b7ef04fd968a92c3 | |
parent | cc550c2d630d27166f0b7e9b085926d3b5582f4c (diff) | |
download | ghdl-e918d6e9030ac611ecd9c9c78b31c3c742c7cc13.tar.gz ghdl-e918d6e9030ac611ecd9c9c78b31c3c742c7cc13.tar.bz2 ghdl-e918d6e9030ac611ecd9c9c78b31c3c742c7cc13.zip |
testsuite/synth: add a test for dyn_insert expand.
-rw-r--r-- | testsuite/synth/memmux01/tb_memmux01.vhdl | 70 | ||||
-rwxr-xr-x | testsuite/synth/memmux01/testsuite.sh | 2 |
2 files changed, 71 insertions, 1 deletions
diff --git a/testsuite/synth/memmux01/tb_memmux01.vhdl b/testsuite/synth/memmux01/tb_memmux01.vhdl new file mode 100644 index 000000000..f81759428 --- /dev/null +++ b/testsuite/synth/memmux01/tb_memmux01.vhdl @@ -0,0 +1,70 @@ +entity tb_memmux01 is +end tb_memmux01; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_memmux01 is + signal wen : std_logic; + signal addr : std_logic_vector (3 downto 0); + signal wdat : std_logic; + signal rdat : std_logic_vector (15 downto 0); + signal clk : std_logic; + signal rst : std_logic; +begin + dut : entity work.memmux01 + port map ( + wen => wen, + addr => addr, + wdat => wdat, + rdat => rdat, + clk => clk, + rst => rst); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + variable v : std_logic_vector(15 downto 0); + begin + rst <= '1'; + wen <= '0'; + wdat <= '1'; + addr <= x"0"; + pulse; + + rst <= '0'; + addr <= x"4"; + wen <= '1'; + pulse; + assert rdat = x"0000" severity failure; + + addr <= x"f"; + pulse; + assert rdat = x"0010" severity failure; + + addr <= x"4"; + wdat <= '0'; + pulse; + assert rdat = x"8010" severity failure; + + pulse; + assert rdat = x"8000" severity failure; + + v := x"8000"; + wdat <= '1'; + for i in 0 to 14 loop + addr <= std_logic_vector(to_unsigned(i, 4)); + pulse; + assert rdat = v severity failure; + v (i) := '1'; + end loop; + + wait; + end process; +end behav; diff --git a/testsuite/synth/memmux01/testsuite.sh b/testsuite/synth/memmux01/testsuite.sh index d3ba44953..a53d09350 100755 --- a/testsuite/synth/memmux01/testsuite.sh +++ b/testsuite/synth/memmux01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in memmux02 memmux03; do +for t in memmux01 memmux02 memmux03; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |