Fixed some ReST issues.

2 files changed, 10 insertions, 10 deletions

diff --git a/doc/getting/PrecompileVendorPrimitives.rst b/doc/getting/PrecompileVendorPrimitives.rst
index d86e9b9b1..04a1010f8 100644
--- a/doc/getting/PrecompileVendorPrimitives.rst
+++ b/doc/getting/PrecompileVendorPrimitives.rst
@@ -152,7 +152,7 @@ Compiling on Windows
 
 * **Step 0 - Configure the scripts (optional)**
 
-    See the next section for how to configure `config.psm1`.
+  See the next section for how to configure `config.psm1`.
 
 * **Step 1 - Browse to your simulation working directory**
 
@@ -173,10 +173,10 @@ Compiling on Windows
 
 * **Step 3 - Viewing the result**
 
-    This creates vendor directories in your current working directory and
-    compiles the vendor files into them.
+  This creates vendor directories in your current working directory and
+  compiles the vendor files into them.
 
-  .. code-block:: PowerShell
+  .. code-block::
 
      PS> dir
          Directory: D:\temp\ghdl
diff --git a/doc/using/ImplementationOfVHDL.rst b/doc/using/ImplementationOfVHDL.rst
index 90b3a56c6..f53b04385 100644
--- a/doc/using/ImplementationOfVHDL.rst
+++ b/doc/using/ImplementationOfVHDL.rst
@@ -128,15 +128,15 @@ You can either use a default clock like this:
 
 .. code-block:: VHDL
 
-    default clock is rising_edge (CLK);
-    assert always
-      a -> eventually! b;
+   default clock is rising_edge (CLK);
+   assert always
+     a -> eventually! b;
 
 or use a clocked expression (note the use of parentheses):
 
-.. code-block:: VHDL
+.. code-block::
 
-    assert (always a -> next[3](b)) @rising_edge(clk);
+   assert (always a -> next[3](b)) @rising_edge(clk);
 
 
 Of course only the simple subset of PSL is allowed.
@@ -201,7 +201,7 @@ PSL vunit files (VHDL-2008 / Synthesis only)
 
 GHDL supports vunit (Verification Unit) files.
 
-.. code-block:: VHDL
+.. code-block::
 
     vunit vunit_name (entity_name(architecture_name))
     {