netlists: remove port_inout.

5 files changed, 10 insertions, 25 deletions

diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 4247c4390..fd25e00f1 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1196,8 +1196,6 @@ package body Netlists.Disp_Vhdl is
                Put ("in");
             when Port_Out =>
                Put ("out");
-            when Port_Inout =>
-               Put ("inout");
          end case;
          Put (' ');
          Put_Type (P.W);
diff --git a/src/synth/netlists-dump.adb b/src/synth/netlists-dump.adb
index 4c0c2b192..c008a1372 100644
--- a/src/synth/netlists-dump.adb
+++ b/src/synth/netlists-dump.adb
@@ -246,8 +246,6 @@ package body Netlists.Dump is
                Put ("input");
             when Port_Out =>
                Put ("output");
-            when Port_Inout =>
-               Put ("inout");
          end case;
          Put (' ');
          Dump_Name (P.Name);
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb
index cc5210f64..a67265030 100644
--- a/src/synth/netlists.adb
+++ b/src/synth/netlists.adb
@@ -698,7 +698,7 @@ package body Netlists is
       end loop;
 
       for O of Output_Descs loop
-         pragma Assert (O.Dir in Port_Outs);
+         pragma Assert (O.Dir = Port_Out);
          Port_Desc_Table.Append (O);
       end loop;
    end Set_Port_Desc;
diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads
index 08297a9f2..c85336385 100644
--- a/src/synth/netlists.ads
+++ b/src/synth/netlists.ads
@@ -123,10 +123,7 @@ package Netlists is
    subtype Width is Uns32;
    No_Width : constant Width := 0;
 
-   type Port_Kind is (Port_In, Port_Out, Port_Inout);
-
-   --  Inout are considered as output.
-   subtype Port_Outs is Port_Kind range Port_Out .. Port_Inout;
+   type Port_Kind is (Port_In, Port_Out);
 
    --  Each module has a numeric identifier that can be used to easily identify
    --  a module.  Gates (and, or, ...) have reserved identifiers.
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index c0277b569..ad2cd73fb 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -198,8 +198,7 @@ package body Synth.Insts is
             when Port_In =>
                Val := Create_Value_Net (No_Net, Inter_Typ);
                Nbr_Inputs := Nbr_Inputs + 1;
-            when Port_Out
-              | Port_Inout =>
+            when Port_Out =>
                Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
                Nbr_Outputs := Nbr_Outputs + 1;
          end case;
@@ -229,8 +228,7 @@ package body Synth.Insts is
                   Nbr_Inputs := Nbr_Inputs + 1;
                   Inports (Nbr_Inputs) :=
                     Make_Port_Desc (Syn_Inst, Inter, Port_In);
-               when Port_Out
-                 | Port_Inout =>
+               when Port_Out =>
                   Nbr_Outputs := Nbr_Outputs + 1;
                   Outports (Nbr_Outputs) :=
                     Make_Port_Desc (Syn_Inst, Inter, Port_Out);
@@ -510,8 +508,7 @@ package body Synth.Insts is
                     (Get_Input (Inst, Nbr_Inputs),
                      Syn_Inst, Assoc, Inst_Obj.Syn_Inst, Inter);
                   Nbr_Inputs := Nbr_Inputs + 1;
-               when Port_Out
-                 | Port_Inout =>
+               when Port_Out =>
                   Synth_Output_Assoc
                     (Get_Output (Inst, Nbr_Outputs),
                      Syn_Inst, Assoc, Inst_Obj.Syn_Inst, Inter);
@@ -643,8 +640,7 @@ package body Synth.Insts is
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
                Val := Create_Value_Net (No_Net, Inter_Typ);
-            when Port_Out
-              | Port_Inout =>
+            when Port_Out =>
                Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
          end case;
          Create_Object (Sub_Inst, Inter, Val);
@@ -794,8 +790,7 @@ package body Synth.Insts is
                   Create_Object (Comp_Inst, Assoc_Inter,
                                  Synth_Expression_With_Type
                                    (Syn_Inst, Actual, Inter_Type));
-               when Port_Out
-                 | Port_Inout =>
+               when Port_Out =>
                   Create_Wire_Object (Comp_Inst, Wire_None, Assoc_Inter);
                   Create_Component_Wire
                     (Assoc_Inter, Get_Value (Comp_Inst, Assoc_Inter));
@@ -880,8 +875,7 @@ package body Synth.Insts is
             case Mode_To_Port_Kind (Get_Mode (Inter)) is
                when Port_In =>
                   null;
-               when Port_Out
-                 | Port_Inout =>
+               when Port_Out =>
                   if Actual /= Null_Node then
                      Port := Get_Output (Inst, Nbr_Outputs);
                      Port := Builders.Build_Port (Get_Build (Syn_Inst), Port);
@@ -1007,8 +1001,7 @@ package body Synth.Insts is
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
                Val := Create_Value_Net (No_Net, Inter_Typ);
-            when Port_Out
-              | Port_Inout =>
+            when Port_Out =>
                Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
          end case;
          Create_Object (Syn_Inst, Inter, Val);
@@ -1156,8 +1149,7 @@ package body Synth.Insts is
             when Port_In =>
                Create_Input_Wire (Self_Inst, Nbr_Inputs, Val);
                Nbr_Inputs := Nbr_Inputs + 1;
-            when Port_Out
-              | Port_Inout =>
+            when Port_Out =>
                Create_Output_Wire (Self_Inst, Inter, Nbr_Outputs, Val);
                Nbr_Outputs := Nbr_Outputs + 1;
          end case;