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authorTristan Gingold <tgingold@free.fr>2019-07-09 19:50:00 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-09 19:50:00 +0200
commitf24e92d2cefff069acf6e5cc6954432f09889dae (patch)
treee31d9e71a38a54b011ee5d7162064063a64eecf4
parentcbcaf392226786aee517d5fe4af3e77fddc23d80 (diff)
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vhdl-sem_lib: free_dependencies: only free entity aspect.
-rw-r--r--src/vhdl/vhdl-sem_lib.adb22
1 files changed, 19 insertions, 3 deletions
diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb
index c09f1a7a2..4bd8363d2 100644
--- a/src/vhdl/vhdl-sem_lib.adb
+++ b/src/vhdl/vhdl-sem_lib.adb
@@ -150,12 +150,28 @@ package body Vhdl.Sem_Lib is
procedure Free_Dependence_List (Design : Iir_Design_Unit)
is
List : Iir_List;
+ It : List_Iterator;
+ El : Iir;
begin
List := Get_Dependence_List (Design);
- if List /= Null_Iir_List then
- Free_Recursive_List (List);
- Destroy_Iir_List (List);
+ if List = Null_Iir_List then
+ return;
end if;
+
+ It := List_Iterate (List);
+ while Is_Valid (It) loop
+ El := Get_Element (It);
+ case Get_Kind (El) is
+ when Iir_Kind_Design_Unit =>
+ null;
+ when Iir_Kind_Entity_Aspect_Entity =>
+ Free_Recursive (El);
+ when others =>
+ Error_Kind ("free_dependence_list", El);
+ end case;
+ Next (It);
+ end loop;
+ Destroy_Iir_List (List);
end Free_Dependence_List;
procedure Load_Parse_Design_Unit (Design_Unit: Iir_Design_Unit; Loc : Iir)