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author | Tristan Gingold <tgingold@free.fr> | 2020-01-01 12:32:22 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-01 12:32:22 +0100 |
commit | f7ce513f49ea7215128e90a8419fdad7cb1a6cc4 (patch) | |
tree | 1d471375e2d7fc7c9335bd4f035cc2d3eb1ffae6 | |
parent | f171b7a717b3cb576a36a87bdd72eb8169e24f91 (diff) | |
download | ghdl-f7ce513f49ea7215128e90a8419fdad7cb1a6cc4.tar.gz ghdl-f7ce513f49ea7215128e90a8419fdad7cb1a6cc4.tar.bz2 ghdl-f7ce513f49ea7215128e90a8419fdad7cb1a6cc4.zip |
testsuite/synth: add a case for #1062
-rw-r--r-- | testsuite/synth/issue1062/ent.vhdl | 16 | ||||
-rw-r--r-- | testsuite/synth/issue1062/tb_ent.vhdl | 19 | ||||
-rwxr-xr-x | testsuite/synth/issue1062/testsuite.sh | 12 |
3 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/synth/issue1062/ent.vhdl b/testsuite/synth/issue1062/ent.vhdl new file mode 100644 index 000000000..acbcac7fe --- /dev/null +++ b/testsuite/synth/issue1062/ent.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + generic (gen1 : natural; + genb : boolean := false; + genv : std_logic_vector(7 downto 0) := "00001111"; + gens : string); + port (d : out std_logic); +end ent; + +architecture behav of ent is +begin + d <= '1' when gen1 = 5 and genb and (gens = "TRUE") + else '0'; +end behav; diff --git a/testsuite/synth/issue1062/tb_ent.vhdl b/testsuite/synth/issue1062/tb_ent.vhdl new file mode 100644 index 000000000..b713bebd1 --- /dev/null +++ b/testsuite/synth/issue1062/tb_ent.vhdl @@ -0,0 +1,19 @@ +entity tb_ent is +end tb_ent; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent is + signal a : std_logic; +begin + dut: entity work.ent + port map (a); + + process + begin + wait for 1 ns; + assert a = '0' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1062/testsuite.sh b/testsuite/synth/issue1062/testsuite.sh new file mode 100755 index 000000000..2fcf72e02 --- /dev/null +++ b/testsuite/synth/issue1062/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in ent; do + synth -ggen1=5 -ggens=TRUE $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |