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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 07:41:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 07:41:07 +0200 |
| commit | fe07ef095be4c8bc0e1f6e6d8eb94692c27445c7 (patch) | |
| tree | 573746d8b6418e3ba7d8c1869085bcb03f24c014 | |
| parent | 8c367d78bc621b9f339042f5d456da94dd0b7861 (diff) | |
| download | ghdl-fe07ef095be4c8bc0e1f6e6d8eb94692c27445c7.tar.gz ghdl-fe07ef095be4c8bc0e1f6e6d8eb94692c27445c7.tar.bz2 ghdl-fe07ef095be4c8bc0e1f6e6d8eb94692c27445c7.zip | |
simul: handle last_value attribute
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 24 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 7 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.ads | 1 |
3 files changed, 31 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index cba9520c4..6b78d4ab8 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1905,7 +1905,7 @@ package body Simul.Vhdl_Simul is type Read_Signal_Enum is ( --- Read_Signal_Last_Value, + Read_Signal_Last_Value, -- For conversion functions. Read_Signal_Driving_Value, @@ -1932,6 +1932,8 @@ package body Simul.Vhdl_Simul is Write_Ghdl_Value (Val, S.Driving_Value); when Read_Signal_Effective_Value => Write_Ghdl_Value (Val, S.Value_Ptr.all); + when Read_Signal_Last_Value => + Write_Ghdl_Value (Val, S.Last_Value); end case; when Type_Vector | Type_Array => @@ -1961,6 +1963,24 @@ package body Simul.Vhdl_Simul is end case; end Exec_Read_Signal; + function Exec_Last_Value_Attribute (Inst : Synth_Instance_Acc; + Expr : Node) return Valtyp + is + Pfx : Target_Info; + Res : Valtyp; + S : Memory_Ptr; + begin + Pfx := Synth_Target (Inst, Get_Prefix (Expr)); + + Res := Create_Value_Memory (Pfx.Targ_Type, Expr_Pool'Access); + + S := Sig_Index (Signals_Table.Table (Pfx.Obj.Val.S).Sig, + Pfx.Off.Net_Off); + + Exec_Read_Signal (S, Get_Memtyp (Res), Read_Signal_Last_Value); + return Res; + end Exec_Last_Value_Attribute; + type Write_Signal_Enum is (Write_Signal_Driving_Value, Write_Signal_Effective_Value); @@ -3198,6 +3218,8 @@ package body Simul.Vhdl_Simul is Synth.Vhdl_Expr.Hook_Signal_Expr := Hook_Signal_Expr'Access; Synth.Vhdl_Expr.Hook_Event_Attribute := Exec_Event_Attribute'Access; Synth.Vhdl_Expr.Hook_Active_Attribute := Exec_Active_Attribute'Access; + Synth.Vhdl_Expr.Hook_Last_Value_Attribute := + Exec_Last_Value_Attribute'Access; Synth.Vhdl_Oper.Hook_Bit_Rising_Edge := Exec_Bit_Rising_Edge'Access; Synth.Vhdl_Oper.Hook_Bit_Falling_Edge := Exec_Bit_Falling_Edge'Access; diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index fdbd5c302..eca5b2453 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -2364,6 +2364,13 @@ package body Synth.Vhdl_Expr is end if; Error_Msg_Synth (Syn_Inst, Expr, "active attribute not allowed"); return No_Valtyp; + when Iir_Kind_Last_Value_Attribute => + if Hook_Last_Value_Attribute /= null then + return Hook_Last_Value_Attribute (Syn_Inst, Expr); + end if; + Error_Msg_Synth (Syn_Inst, Expr, + "last_value attribute not allowed"); + return No_Valtyp; when Iir_Kind_Dot_Attribute => if Hook_Dot_Attribute /= null then return Hook_Dot_Attribute (Syn_Inst, Expr); diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads index d4b27dc05..941bae57b 100644 --- a/src/synth/synth-vhdl_expr.ads +++ b/src/synth/synth-vhdl_expr.ads @@ -89,6 +89,7 @@ package Synth.Vhdl_Expr is function (Syn_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp; Hook_Event_Attribute : Hook_Attribute_Acc; Hook_Active_Attribute : Hook_Attribute_Acc; + Hook_Last_Value_Attribute : Hook_Attribute_Acc; Hook_Dot_Attribute : Hook_Attribute_Acc; -- Use base type of EXPR to synthesize EXPR. Useful when the type of |