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| author | umarcor <unai.martinezcorral@ehu.eus> | 2022-02-07 19:28:23 +0100 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2022-02-07 19:41:40 +0100 |
| commit | 6a694dd839a18cdf0382753fffc17aa1fbd41f9d (patch) | |
| tree | e7330a6cd6d87f80d63cc846100175b4817682bf /doc/about.rst | |
| parent | ea18eb25e53567a979d40d6cc2d69e1d3e289c93 (diff) | |
| download | ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.tar.gz ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.tar.bz2 ghdl-6a694dd839a18cdf0382753fffc17aa1fbd41f9d.zip | |
doc: use extlinks more
Diffstat (limited to 'doc/about.rst')
| -rw-r--r-- | doc/about.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/about.rst b/doc/about.rst index 388e75d15..413a8348d 100644 --- a/doc/about.rst +++ b/doc/about.rst @@ -99,7 +99,7 @@ Several third party projects are supported: `Yosys <https://github.com/YosysHQ/yosys>`__ (through the `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`__) `cocotb <https://github.com/potentialventures/cocotb>`__, -(through the `VPI interface <https://en.wikipedia.org/wiki/Verilog_Procedural_Interface>`__), +(through the :wikipedia:`VPI interface <Verilog_Procedural_Interface>`), `VUnit <https://vunit.github.io/>`__, `OSVVM <http://osvvm.org/>`__, :doc:`vhdlmodel:index`, |