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authorumarcor <unai.martinezcorral@ehu.eus>2022-02-07 19:28:23 +0100
committerumarcor <unai.martinezcorral@ehu.eus>2022-02-07 19:41:40 +0100
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Diffstat (limited to 'doc/quick_start/simulation/heartbeat')
-rw-r--r--doc/quick_start/simulation/heartbeat/index.rst17
1 files changed, 10 insertions, 7 deletions
diff --git a/doc/quick_start/simulation/heartbeat/index.rst b/doc/quick_start/simulation/heartbeat/index.rst
index e95145095..57e348e89 100644
--- a/doc/quick_start/simulation/heartbeat/index.rst
+++ b/doc/quick_start/simulation/heartbeat/index.rst
@@ -4,14 +4,16 @@
`Heartbeat` module
==================
-Although :ref:`Hello world <QuickStart:hello>` illustrates that `VHDL` is supported as a general purpose language, the main use case
-of `GHDL` is to simulate hardware descriptions. The following block, which is saved in a file named
-:file:`heartbeat.vhdl`, is an example of how to generate a 100 MHz clock signal with non-synthesisable VHDL:
+Although :ref:`Hello world <QuickStart:hello>` illustrates that `VHDL` is supported as a general purpose language, the
+main use case of `GHDL` is to simulate hardware descriptions.
+The following block, which is saved in a file named :file:`heartbeat.vhdl`, is an example of how to generate a 100 MHz
+clock signal with non-synthesisable VHDL:
.. literalinclude:: heartbeat.vhdl
:language: vhdl
-It can be :ref:`analysed <Analysis:command>`, :ref:`elaborated <Elaboration:command>` and :ref:`run <Run:command>`, as you already know:
+It can be :ref:`analysed <Analysis:command>`, :ref:`elaborated <Elaboration:command>` and :ref:`run <Run:command>`, as
+you already know:
.. code-block:: shell
@@ -21,7 +23,7 @@ It can be :ref:`analysed <Analysis:command>`, :ref:`elaborated <Elaboration:comm
However, execution of the design does not terminate. At the same time, no output is shown on screen. This is because,
traditionally, hardware designs are continuously running devices which do not have a screen where to print. In this
-context, inspection and verification of the behaviour is done through `waveforms <https://en.wikipedia.org/wiki/Waveform_viewer>`_,
+context, inspection and verification of the behaviour is done through :wikipedia:`waveforms <Waveform_viewer>`,
which is supported by `GHDL` (see :ref:`export_waves`). You can use either :option:`--wave`, :option:`--vcd`,
:option:`--vcdgz` or :option:`--fst` to save the signals of the simulation to a file. Then, terminate the execution
(:kbd:`C-c`) and you can inspect the wave with a viewer, such as `GtkWave <http://gtkwave.sourceforge.net/>`_. As
@@ -38,5 +40,6 @@ Then, you can view the dump:
gtkwave wave.ghw
-Of course, manually terminating the simulation is for illustration purposes only. In :ref:`Full adder <QuickStart:adder>` and
-:ref:`QuickStart:DLX`, you will see how to write a testbench to terminate the simulation programmatically.
+Of course, manually terminating the simulation is for illustration purposes only.
+In :ref:`Full adder <QuickStart:adder>` and :ref:`QuickStart:DLX`, you will see how to write a testbench to terminate
+the simulation programmatically.