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author | gritbub <38131016+gritbub@users.noreply.github.com> | 2018-05-18 17:26:51 -0500 |
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committer | gritbub <38131016+gritbub@users.noreply.github.com> | 2018-06-01 14:18:09 -0500 |
commit | 8122c18944b69305060b03fad5b5a46ca59c0975 (patch) | |
tree | 5bd329ebfcdc411b35372fba2873269acea2c1d7 /doc/references | |
parent | e135fe7fbe1a79256f6f4ab2c5a5cd1666166197 (diff) | |
download | ghdl-8122c18944b69305060b03fad5b5a46ca59c0975.tar.gz ghdl-8122c18944b69305060b03fad5b5a46ca59c0975.tar.bz2 ghdl-8122c18944b69305060b03fad5b5a46ca59c0975.zip |
Rephrase documentation - typos, grammatical nuance, and links
Diffstat (limited to 'doc/references')
-rw-r--r-- | doc/references/CodingStyle.rst | 10 | ||||
-rw-r--r-- | doc/references/CommandReference.rst | 22 | ||||
-rw-r--r-- | doc/references/ImplementationOfVHDL.rst | 56 | ||||
-rw-r--r-- | doc/references/ImplementationOfVITAL.rst | 12 |
4 files changed, 50 insertions, 50 deletions
diff --git a/doc/references/CodingStyle.rst b/doc/references/CodingStyle.rst index 3c9b9f398..2fb09c6ef 100644 --- a/doc/references/CodingStyle.rst +++ b/doc/references/CodingStyle.rst @@ -12,9 +12,9 @@ We try to follow the 'GNU Coding Standards' when possible: comments before declarations, two spaces at end of sentences, finish sentences with a dot. But: 3 spaces for indentation. -No trailing spaces, not TAB (HT). +No trailing spaces, no TAB (HT). -Subprograms must have a comment before to describe it, like: +Subprograms must have a comment before to describe them, like: .. code-block:: Ada @@ -74,9 +74,9 @@ declaration). Don't repeat the comment before the subprogram body. Loc : Iir) return O_Enode - 7) If not possible, ask yourself what is wrong! Shorten a name. + 7. If not possible, ask yourself what is wrong! Shorten a name. -* Rule for the 'is': one a new line only if the declarative part is not empty: +* Rule for the 'is': on a new line only if the declarative part is not empty: .. code-block:: Ada @@ -92,7 +92,7 @@ declaration). Don't repeat the comment before the subprogram body. function Translate_Static_Range_Dir (Expr : Iir) return O_Cnode is begin - If the parametere line is too long with the 'is', put in on a separate line: + If the parameter line is too long with the 'is', put in on a separate line: .. code-block:: Ada diff --git a/doc/references/CommandReference.rst b/doc/references/CommandReference.rst index 16430cb72..06fdb7396 100644 --- a/doc/references/CommandReference.rst +++ b/doc/references/CommandReference.rst @@ -25,7 +25,7 @@ Help [``-h``] Display (on the standard output) a short description of the all the commands available. If the help switch is followed by a command switch, then options -for this later command are displayed:: +for that second command are displayed:: ghdl --help ghdl -h @@ -57,7 +57,7 @@ Version [``--version``] .. option:: --version, -v -Display the GHDL version and exit. +Display the GHDL version. File commands ============= @@ -72,7 +72,7 @@ Pretty print [``--pp-html``] .. option:: --pp-html <[options] file...> -The files are just scanned and an html file, with syntax highlighting is generated on standard output. Since the files are not even parsed, erroneous files or incomplete designs can be pretty printed. +The files are just scanned and an html file with syntax highlighting is generated on standard output. Since the files are not even parsed, erroneous files or incomplete designs can be pretty printed. The style of the html file can be modified with the :option:`--format=` option: @@ -86,7 +86,7 @@ Find [``-f``] .. option:: -f <file...> -The files are scanned, parsed and the names of design units are displayed. Design units marked with two stars are candidate to be at the apex of a design hierarchy. +The files are scanned, parsed and the names of design units are displayed. Design units marked with two stars are candidates to be at the apex of a design hierarchy. .. index:: cmd file chop @@ -95,9 +95,9 @@ Chop [``--chop``] .. option:: --chop <files...> -The provided files are read, and a file is written in the current directory for every design unit. Each filename is build according to the type: +The provided files are read, and a file is written in the current directory for every design unit. Each filename is built according to the type: -* For an entity declaration, a package declaration or a configuration the file name is :file:`NAME.vhdl`, where `NAME` is the name of the design unit. +* For an entity declaration, a package declaration, or a configuration the file name is :file:`NAME.vhdl`, where `NAME` is the name of the design unit. * For a package body, the filename is :file:`NAME-body.vhdl`. * Finally, for an architecture `ARCH` of an entity `ENTITY`, the filename is :file:`ENTITY-ARCH.vhdl`. @@ -105,7 +105,7 @@ Since the input files are parsed, this command aborts in case of syntax error. T Comments between design units are stored into the most adequate files. -This command may be useful to split big files, if your computer has not enough memory to compile such files. The size of the executable is reduced too. +This command may be useful to split big files, if your computer doesn't have enough memory to compile such files. The size of the executable is reduced too. .. index:: cmd file lines @@ -126,7 +126,7 @@ Bind [``--bind``] .. option:: --bind <[options] primary_unit [secondary_unit]> -Performs only the first stage of the elaboration command; the list of objects files is created but the executable is not built. This command should be used only when the main entry point is not GHDL. +Performs only the first stage of the elaboration command; the list of object files is created but the executable is not built. This command should be used only when the main entry point is not GHDL. .. index:: cmd GCC/LLVM linking @@ -151,15 +151,15 @@ Options .. option:: --mb-comments, -C -Allow multi-bytes chars in a comment +Allow multi-bytes chars in a comment. .. option:: --syn-binding Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name. -This rule is known as synthesizer rule. +This rule is known as the synthesizer rule. -There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known library. A known library is a library which has been named in your design. +There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known libraries. A known library is a library which has been named in your design. This option is only useful during elaboration. diff --git a/doc/references/ImplementationOfVHDL.rst b/doc/references/ImplementationOfVHDL.rst index 66246608d..4aa8b3a71 100644 --- a/doc/references/ImplementationOfVHDL.rst +++ b/doc/references/ImplementationOfVHDL.rst @@ -4,7 +4,7 @@ Implementation of VHDL *************************** -This chapter describes several implementation defined aspect of VHDL in GHDL. +This chapter describes several implementation defined aspects of VHDL in GHDL. .. _VHDL_standards: @@ -33,7 +33,7 @@ VHDL standards .. index:: v08 -This is very unfortunate, but there are many versions of the VHDL +Unfortunately, there are many versions of the VHDL language, and they aren't backward compatible. The VHDL language was first standardized in 1987 by IEEE as IEEE 1076-1987, and @@ -64,7 +64,7 @@ standard is not fully backward compatible with VHDL-93, since the type of a shared variable must now be a protected type (there was no such restriction before). -Minors corrections were added by the 2002 revision of the VHDL standard. This +Minor corrections were added by the 2002 revision of the VHDL standard. This revision is not fully backward compatible with VHDL-00 since, for example, the value of the `'instance_name` attribute has slightly changed. @@ -96,12 +96,12 @@ table below: Select VHDL-2000 standard, which adds protected types. 02 - Select VHDL-2002 standard + Select VHDL-2002 standard. 08 Select VHDL-2008 standard (partially implemented). -The 93, 93c, 00 and 02 standards are considered as compatible: you can +The 93, 93c, 00 and 02 standards are considered compatible: you can elaborate a design mixing these standards. However, 87, 93 and 08 are not compatible. @@ -121,7 +121,7 @@ with the `psl` keyword. The keyword must be followed (on the same line) by a PSL keyword such as `assert` or `default`. To continue a PSL statement on the next line, just start a new comment. -A PSL statement is considered as a process. So it is not allowed within +A PSL statement is considered a process, so it's not allowed within a process. All PSL assertions must be clocked (GHDL doesn't support unclocked assertion). @@ -135,7 +135,7 @@ You can either use a default clock like this: -- psl assert always -- a -> eventually! b; -or use a clocked expression (note the use of parenthesis): +or use a clocked expression (note the use of parentheses): .. code-block:: VHDL @@ -150,7 +150,7 @@ Source representation ===================== According to the VHDL standard, design units (i.e. entities, -architectures, packages, package bodies and configurations) may be +architectures, packages, package bodies, and configurations) may be independently analyzed. Several design units may be grouped into a design file. @@ -164,9 +164,9 @@ GHDL does not impose any restriction on the name of a design file (except that the filename may not contain any control character or spaces). -GHDL do not keep a binary representation of the design units analyzed like +GHDL does not keep a binary representation of the design units analyzed like other VHDL analyzers. The sources of the design units are re-read when -needed (for example, an entity is re-read when one of its architecture is +needed (for example, an entity is re-read when one of its architectures is analyzed). Therefore, if you delete or modify a source file of a unit analyzed, GHDL will refuse to use it. @@ -199,7 +199,7 @@ There are some restrictions on the entity being at the apex of a design hierarchy: * The generic must have a default value, and the value of a generic is its - default value; + default value. * The ports type must be constrained. Using vendor libraries @@ -230,7 +230,7 @@ Interfacing to other languages Interfacing with foreign languages is possible only on GNU/Linux systems. You can define a subprogram in a foreign language (such as `C` or -`Ada`) and import it in a VHDL design. +`Ada`) and import it into a VHDL design. Foreign declarations -------------------- @@ -264,7 +264,7 @@ subprogram and must be after it. This is a general rule for specifications. The value of the specification must be a locally static string. Even when a subprogram is foreign, its body must be present. However, since -it won't be called, you can made it empty or simply but an assertion. +it won't be called, you can make it empty or simply put an assertion. The value of the attribute must start with ``VHPIDIRECT`` (an upper-case keyword followed by one or more blanks). The linkage name of the @@ -277,24 +277,24 @@ Restrictions on foreign declarations Any subprogram can be imported. GHDL puts no restrictions on foreign subprograms. However, the representation of a type or of an interface in a -foreign language may be obscure. Most of non-composite types are easily imported: +foreign language may be obscure. Most non-composite types are easily imported: *integer types* - They are represented on a 32 bits word. This generally corresponds to + They are represented by a 32 bit word. This generally corresponds to `int` for `C` or `Integer` for `Ada`. *physical types* - They are represented on a 64 bits word. This generally corresponds to the + They are represented by a 64 bit word. This generally corresponds to the `long long` for `C` or `Long_Long_Integer` for `Ada`. *floating point types* - They are represented on a 64 bits floating point word. This generally + They are represented by a 64 bit floating point word. This generally corresponds to `double` for `C` or `Long_Float` for `Ada`. *enumeration types* - They are represented on 8 bits or 32 bits word, if the number of literals is - greater than 256. There is no corresponding C types, since arguments are + They are represented by an 8 bit word, or, if the number of literals is + greater than 256, by a 32 bit word. There is no corresponding C type, since arguments are not promoted. Non-composite types are passed by value. For the `in` mode, this @@ -310,12 +310,12 @@ to subprograms. Arrays with static bounds are represented like a `C` array, whose length is the number of elements, and are passed by reference to subprograms. -Unconstrained array are represented by a fat pointer. Do not use unconstrained +Unconstrained arrays are represented by a fat pointer. Do not use unconstrained arrays in foreign subprograms. -Accesses to an unconstrained array is a fat pointer. Other accesses correspond to an address and are passed to a subprogram like other non-composite types. +Accesses to an unconstrained array are fat pointers. Other accesses correspond to an address and are passed to a subprogram like other non-composite types. -Files are represented by a 32 bits word, which corresponds to an index +Files are represented by a 32 bit word, which corresponds to an index in a table. .. _Linking_with_foreign_object_files: @@ -324,7 +324,7 @@ Linking with foreign object files --------------------------------- You may add additional files or options during the link using the -*-Wl,* of `GHDL`, as described in :ref:`Elaboration_command`. +*-Wl,* of `GHDL`, as described in ':ref:`Elaboration:command`'. For example:: ghdl -e -Wl,-lm math_tb @@ -386,7 +386,7 @@ design apex is ``design``. $ ghdl --bind design -Finally, compile, bind your `Ada` program at link it with your `VHDL` +Finally, compile, bind your `Ada` program and link it with your `VHDL` design:: $ gnatmake my_prog -largs `ghdl --list-link design` @@ -396,9 +396,9 @@ Using GRT from Ada ------------------ .. warning:: - This topic is only for advanced users knowing how to use `Ada` - and `GNAT`. This is provided only for reference, I have tested - this once before releasing `GHDL` 0.19 but this is not checked at + This topic is only for advanced users who know how to use `Ada` + and `GNAT`. This is provided only for reference; I have tested + this once before releasing `GHDL` 0.19, but this is not checked at each release. The simulator kernel of `GHDL` named :dfn:`GRT` is written in @@ -434,7 +434,7 @@ tested this step. You are now ready to use it. -For example, here is an example, :file:`test_grt.adb` which displays the top +Here is an example, :file:`test_grt.adb` which displays the top level design name. .. code-block:: Ada diff --git a/doc/references/ImplementationOfVITAL.rst b/doc/references/ImplementationOfVITAL.rst index 3cf99663c..a3e0aeb98 100644 --- a/doc/references/ImplementationOfVITAL.rst +++ b/doc/references/ImplementationOfVITAL.rst @@ -11,7 +11,7 @@ Implementation of VITAL .. index:: 1076.4 This chapter describes how VITAL is implemented in GHDL. Support of VITAL is -really in a preliminary stage. Do not expect too much of it as now. +really in a preliminary stage. Do not expect too much of it as of right now. .. _vital_packages: @@ -28,7 +28,7 @@ requirements of VITAL: VITAL 1995 requires the models follow the VHDL 1987 standard, while VITAL 2000 requires the models follow VHDL 1993. The VITAL 2000 packages were slightly modified so that they conform to -the VHDL 1993 standard (a few functions are made pure and a few one +the VHDL 1993 standard (a few functions are made pure and a few impure). .. _vhdl_restrictions_for_vital: @@ -65,8 +65,8 @@ Backannotation information provided by an external files. The external files must be SDF (Standard Delay Format) files. GHDL -supports a tiny subset of SDF version 2.1, other version number can be -used, provided no features added by the next version are used. +supports a tiny subset of SDF version 2.1. Other version numbers can be +used, provided no features added by later versions are used. Hierarchical instance names are not supported. However you can use a list of instances. If there is no instance, the top entity will be annotated and @@ -86,8 +86,8 @@ release. Negative constraint calculation =============================== -Negative constraint delay adjustment are necessary to handle negative -constraint such as a negative setup time. This step is defined in the VITAL +Negative constraint delay adjustments are necessary to handle negative +constraints such as a negative setup time. This step is defined in the VITAL standard and should occur after backannotation. GHDL does not do negative constraint calculation. It fails to handle models |