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author | Patrick Lehmann <Patrick.Lehmann@tu-dresden.de> | 2017-03-04 18:47:08 +0100 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2017-12-10 12:02:05 +0100 |
commit | 7b2b91900e8217fd75fcc755f14c5f098662f1f8 (patch) | |
tree | a627a96ad6af99e0ec38b6ab6d6dad2c6e35c0ce /doc/using/Simulation.rst | |
parent | 660998b341f810b8a37fed12cbf00e8d301ec3d7 (diff) | |
download | ghdl-7b2b91900e8217fd75fcc755f14c5f098662f1f8.tar.gz ghdl-7b2b91900e8217fd75fcc755f14c5f098662f1f8.tar.bz2 ghdl-7b2b91900e8217fd75fcc755f14c5f098662f1f8.zip |
Fixed typos, indentation and headline underlining.
Diffstat (limited to 'doc/using/Simulation.rst')
-rw-r--r-- | doc/using/Simulation.rst | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst index 5445bc830..5945588df 100644 --- a/doc/using/Simulation.rst +++ b/doc/using/Simulation.rst @@ -2,12 +2,12 @@ .. _USING:Simulation: Simulation and runtime -********************** +###################### .. _simulation_options: Simulation options -============ +================== In most system environments, it is possible to pass options while invoking a program. Contrary to most programming languages, there is no @@ -109,7 +109,7 @@ all options available, including the debugging one. .. _export_waves: Export waveforms -============ +================ .. option:: --read-opt-file<=FILENAME> @@ -231,7 +231,7 @@ Export waveforms - `Source code annotation is currently not available for VHDL, however all of GTKWave's other debug features are readily accessible. VHDL support is planned for a future release`. That's something that could be added in the future, but I have no plan for it. Export hierarchy and references -============ +=============================== .. option:: --disp-tree<[=KIND]> @@ -274,20 +274,21 @@ The set of :samp:`file` are analyzed, and then, if the analysis is successful, h Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but still being human readable. .. TODO:: - * Maybe worth adding a small example of how to generate a JSON file? + * Maybe worth adding a small example of how to generate a JSON file? .. option:: --file-to-xml Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation... .. WARNING:: - * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping. - * Note that at this time there is no XML dump of the elaborated design. + * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping. + * Note that at this time there is no XML dump of the elaborated design. + .. index:: debugging Debugging -============ +========= .. option:: --trace-signals @@ -338,7 +339,7 @@ Dump Run Time Information (RTI). Allow :samp:`--work=std` GNU Debugger (GDB) -------------------- +------------------ .. index:: `__ghdl_fatal` |