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author | Tristan Gingold <tgingold@free.fr> | 2018-12-12 18:25:50 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-12-13 18:50:56 +0100 |
commit | 943fc68ec25a1a30666a6630d163ddff35d25b52 (patch) | |
tree | e89f216600527ee791beb5eb38a0ca9f25469748 /doc/using/Simulation.rst | |
parent | 9f22a5ebaf00ca4c7c2500e550047aa72b31fbcf (diff) | |
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parse_psl: also convert and/or from PSL to vhdl.
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