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authorTristan Gingold <tgingold@free.fr>2021-04-28 21:21:28 +0200
committerTristan Gingold <tgingold@free.fr>2021-04-28 21:39:05 +0200
commit6bc0f927f803debc51d5bb9bed46cf18b5a0435c (patch)
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parent4f7aaa50f93b667aee662de5f9308545bb00a5f2 (diff)
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synth: add verilog output
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