doc: move -C/--syn-binding doc to InvokingGHDL.

3 files changed, 36 insertions, 20 deletions

diff --git a/doc/using/CommandReference.rst b/doc/using/CommandReference.rst
index f66335d2c..6284db18b 100644
--- a/doc/using/CommandReference.rst
+++ b/doc/using/CommandReference.rst
@@ -142,7 +142,7 @@ Performs only the second stage of the elaboration command: the executable is cre
 .. index:: cmd GCC/LLVM list link
 
 List link [``--list-link``]
--------------------------------
+---------------------------
 
 .. option:: --list-link <primary_unit [secondary_unit]>
 
@@ -154,22 +154,21 @@ This command may be used only after a bind command. GHDL displays all the files
    * Filter the output of ``--list-link`` with e.g. ``sed``.
    * Provide an additional non-anonymous version script: ``-Wl,-Wl,--version-script=file.ver``.
 
-Options
-=======
-
-.. option:: --mb-comments, -C
+.. index:: cmd XML generation
 
-Allow multi-bytes chars in a comment.
+XML tree generation [``--file-to-xml``]
+---------------------------------------
 
-.. option:: --syn-binding
+.. option:: --file-to-xml
 
-Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name.
+  Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation, etc.
 
-This rule is known as the synthesizer rule.
+.. WARNING::
+   * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping.
+   * Note that at this time there is no XML dump of the elaborated design.
 
-There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known libraries. A known library is a library which has been named in your design.
-
-This option is only useful during elaboration.
+Options
+=======
 
 .. option:: --GHDL1<=COMMAND>
 
diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst
index 918acacfd..63af39f08 100644
--- a/doc/using/InvokingGHDL.rst
+++ b/doc/using/InvokingGHDL.rst
@@ -341,6 +341,31 @@ Options
 
   Enable parsing of PSL assertions within comments. See section :ref:`PSL_implementation` for more details.
 
+.. option:: --mb-comments, -C
+
+  Allow UTF8 or multi-bytes chars in a comment.
+
+  According to the VHDL standards before 2002, the only characters
+  allowed in a source file (and that includes the comments) are the
+  graphical characters of the ISO 8859-1 character set.  This is
+  incompatible with comments using UTF-8 or some other encoding.  This
+  option lift this restriction.
+
+.. option:: --syn-binding
+
+  Use synthesizer rules for component binding. During elaboration, if
+  a component is not bound to an entity using VHDL LRM rules, try to
+  find in any known library an entity whose name is the same as the
+  component name.
+
+  This rule is known as the synthesizer rule.
+
+  There are two key points: normal VHDL LRM rules are tried first and
+  entities are searched only in known libraries. A known library is a
+  library which has been named in your design.
+
+  This option is only useful during elaboration.
+
 .. option:: --format=<FORMAT>
 
   Define the output format of some options, such as :option:`--pp-html` or :option:`--xref-html`.
diff --git a/doc/using/Simulation.rst b/doc/using/Simulation.rst
index 81f64e9ed..c73a379d8 100644
--- a/doc/using/Simulation.rst
+++ b/doc/using/Simulation.rst
@@ -299,11 +299,3 @@ Export hierarchy and references
 .. option:: --psl-report=<FILENAME>
 
   Write a report for PSL at the end of simulation. For each PSL cover and assert statements, the name, source location and whether it passed or failed is reported. The file is written using the JSON format, but is still human readable.
-
-.. option:: --file-to-xml
-
-  Outputs an XML representation of the decorated syntax tree for the input file and its dependencies. It can be used for VHDL tooling using semantic information, like style checkers, documentation extraction, complexity estimation, etc.
-
-.. WARNING::
-   * The AST slightly changes from time to time (particularly when new nodes are added for new language features), so be liberal in what is allowed by your tool. Also, the XML can be quite large so consider it only during prototyping.
-   * Note that at this time there is no XML dump of the elaborated design.