openieee: add support of vhdl 2008 (WIP)

4 files changed, 151 insertions, 63 deletions

diff --git a/libraries/openieee/build_1164.py b/libraries/openieee/build_1164.py
index 06f25c30b..393ee92cf 100755
--- a/libraries/openieee/build_1164.py
+++ b/libraries/openieee/build_1164.py
@@ -20,6 +20,11 @@
 import re
 import sys
 
+# Supported versions
+V87=0
+V93=1
+V08=2
+
 binary_funcs = [ "and", "nand", "or", "nor", "xor" ]
 
 # Python modelisation of std_ulogic type.
@@ -101,14 +106,14 @@ def gen_log_table1(name, func):
         w(func (b))
     w('";\n')
 
-def disp_tables():
+def disp_tables(version):
     "Generate logic tables"
     gen_log_table2("and", sl_and)
     gen_log_table2("nand", lambda a,b : sl_not(sl_and(a, b)))
     gen_log_table2("or", sl_or)
     gen_log_table2("nor", lambda a,b : sl_not(sl_or(a,b)))
     gen_log_table2("xor", sl_xor)
-    if "xnor" in binary_funcs:
+    if version >= V93:
         gen_log_table2("xnor", lambda a,b : sl_not(sl_xor(a,b)))
     gen_log_table1("not", sl_not)
 
@@ -167,7 +172,7 @@ def disp_vec_unary(func, typ):
     return res;
   end "{0}";\n""".format(func, typ))
 
-def disp_all_log_funcs():
+def disp_all_log_funcs(version):
     "Generate all function bodies for logic operators"
     for f in binary_funcs:
         disp_scalar_binary(f)
@@ -228,7 +233,7 @@ def disp_sv_to_sv_conv(s,d):
     return res_type (s);
   end to_std{1}vector;\n""".format(s,d))
 
-def disp_all_conv_funcs():
+def disp_all_conv_funcs(version):
     "Generate conversion function bodies"
     for v in vec_types:
         disp_sv_to_bv_conv(v)
@@ -287,7 +292,7 @@ def disp_conv_b_t(typ):
     return bit_to_x01 (b);
   end to_{1};\n""".format(typ, utyp))
 
-def disp_all_norm_funcs():
+def disp_all_norm_funcs(version):
     "Generate all function bodies for conversion"
     for typ in [ "x01", "x01z", "ux01" ]:
         for v in vec_types:
@@ -297,7 +302,7 @@ def disp_all_norm_funcs():
             disp_conv_bv_vec(typ, v)
         disp_conv_b_t(typ)
 
-def disp_all_isx_funcs():
+def disp_all_isx_funcs(version):
     "Generate all function bodies for isx functions"
     for v in vec_types:
         w("""
@@ -328,34 +333,48 @@ pats = {'  @TAB\n' : disp_tables,
 spec_file='std_logic_1164.vhdl'
 proto_file='std_logic_1164-body.proto'
 
-def gen_body():
+def gen_body(filename, version):
+    global out
+    out = open(filename, 'w')
     w('--  This -*- vhdl -*- file was generated from ' + proto_file + '\n')
     for line in open(proto_file):
         if line in pats:
-            pats[line]()
+            pats[line](version)
             continue
         w(line)
+    out.close()
+
+VDICT={'--V87':  lambda x: x == V87,
+       '--!V87': lambda x: x != V87,
+       '--V93':  lambda x: x == V93,
+       '--V08':  lambda x: x == V08,
+       '--!V08': lambda x: x != V08}
+
+def preprocess_line(line, version):
+    for p in VDICT:
+        pos = line.find(p)
+        if pos >= 0:
+            if not VDICT[p](version):
+                return None
+            l = line[:pos].rstrip() + '\n'
+            return l
+    return line
+
+def copy_spec(dest, version):
+    out=open(dest, 'w')
+    for line in open(spec_file):
+        l = preprocess_line(line, version)
+        if l is not None:
+            out.write(l)
+    out.close()
 
 # Copy spec
-out=open('std_logic_1164.v87', 'w')
-for line in open(spec_file):
-    if '"xnor"' in line:
-        w("--" + line[2:])
-    else:
-        w(line)
-out.close()
-
-out=open('std_logic_1164.v93', 'w')
-for line in open(spec_file):
-    w(line)
-out.close()
+copy_spec('std_logic_1164.v87', V87)
+copy_spec('std_logic_1164.v93', V93)
+copy_spec('std_logic_1164.v08', V08)
 
 # Generate bodies
-out=open('std_logic_1164-body.v87', 'w')
-gen_body()
-out.close()
+gen_body('std_logic_1164-body.v87', V87)
 
 binary_funcs.append("xnor")
-out=open('std_logic_1164-body.v93', 'w')
-gen_body()
-out.close()
+gen_body('std_logic_1164-body.v93', V93)
diff --git a/libraries/openieee/std_logic_1164.v87 b/libraries/openieee/std_logic_1164.v87
index 841be73a4..1dc5252fd 100644
--- a/libraries/openieee/std_logic_1164.v87
+++ b/libraries/openieee/std_logic_1164.v87
@@ -16,14 +16,12 @@
 --  along with GCC; see the file COPYING2.  If not see
 --  <http://www.gnu.org/licenses/>.
 
---  This package is valid for VHDL version until but not including 2008.
---  For VHDL87, the functions xnor should be removed.
-
 package std_logic_1164 is
 
   --  Unresolved logic state.
   type std_ulogic is
-    ('U',  --  Uninitialized, this is also the default value.
+    (
+     'U',  --  Uninitialized, this is also the default value.
      'X',  --  Unknown / conflict value (forcing level).
      '0',  --  0 (forcing level).
      '1',  --  1 (forcing level).
@@ -32,7 +30,7 @@ package std_logic_1164 is
      'L',  --  0 (weak level).
      'H',  --  1 (weak level).
      '-'   --  Don't care.
-     );
+    );
 
   --  Vector of logic state.
   type std_ulogic_vector is array (natural range <>) of std_ulogic;
@@ -70,7 +68,6 @@ package std_logic_1164 is
   function "or"   (l : std_ulogic; r : std_ulogic) return UX01;
   function "nor"  (l : std_ulogic; r : std_ulogic) return UX01;
   function "xor"  (l : std_ulogic; r : std_ulogic) return UX01;
---function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;
   function "not"  (l : std_ulogic) return UX01;
 
   --  Logical operators for vectors.
@@ -81,7 +78,6 @@ package std_logic_1164 is
   function "or"   (l, r : std_logic_vector) return std_logic_vector;
   function "nor"  (l, r : std_logic_vector) return std_logic_vector;
   function "xor"  (l, r : std_logic_vector) return std_logic_vector;
---function "xnor" (l, r : std_logic_vector) return std_logic_vector;
   function "not"  (l : std_logic_vector) return std_logic_vector;
 
   function "and"  (l, r : std_ulogic_vector) return std_ulogic_vector;
@@ -89,7 +85,6 @@ package std_logic_1164 is
   function "or"   (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "nor"  (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "xor"  (l, r : std_ulogic_vector) return std_ulogic_vector;
---function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "not"  (l : std_ulogic_vector) return std_ulogic_vector;
 
   --  Conversion functions.
diff --git a/libraries/openieee/std_logic_1164.v93 b/libraries/openieee/std_logic_1164.v93
index b5136f538..876733977 100644
--- a/libraries/openieee/std_logic_1164.v93
+++ b/libraries/openieee/std_logic_1164.v93
@@ -16,14 +16,12 @@
 --  along with GCC; see the file COPYING2.  If not see
 --  <http://www.gnu.org/licenses/>.
 
---  This package is valid for VHDL version until but not including 2008.
---  For VHDL87, the functions xnor should be removed.
-
 package std_logic_1164 is
 
   --  Unresolved logic state.
   type std_ulogic is
-    ('U',  --  Uninitialized, this is also the default value.
+    (
+     'U',  --  Uninitialized, this is also the default value.
      'X',  --  Unknown / conflict value (forcing level).
      '0',  --  0 (forcing level).
      '1',  --  1 (forcing level).
@@ -32,7 +30,7 @@ package std_logic_1164 is
      'L',  --  0 (weak level).
      'H',  --  1 (weak level).
      '-'   --  Don't care.
-     );
+    );
 
   --  Vector of logic state.
   type std_ulogic_vector is array (natural range <>) of std_ulogic;
diff --git a/libraries/openieee/std_logic_1164.vhdl b/libraries/openieee/std_logic_1164.vhdl
index b5136f538..6dec5b3fb 100644
--- a/libraries/openieee/std_logic_1164.vhdl
+++ b/libraries/openieee/std_logic_1164.vhdl
@@ -16,14 +16,12 @@
 --  along with GCC; see the file COPYING2.  If not see
 --  <http://www.gnu.org/licenses/>.
 
---  This package is valid for VHDL version until but not including 2008.
---  For VHDL87, the functions xnor should be removed.
-
 package std_logic_1164 is
 
   --  Unresolved logic state.
   type std_ulogic is
-    ('U',  --  Uninitialized, this is also the default value.
+    (
+     'U',  --  Uninitialized, this is also the default value.
      'X',  --  Unknown / conflict value (forcing level).
      '0',  --  0 (forcing level).
      '1',  --  1 (forcing level).
@@ -32,7 +30,7 @@ package std_logic_1164 is
      'L',  --  0 (weak level).
      'H',  --  1 (weak level).
      '-'   --  Don't care.
-     );
+    );
 
   --  Vector of logic state.
   type std_ulogic_vector is array (natural range <>) of std_ulogic;
@@ -52,7 +50,8 @@ package std_logic_1164 is
   subtype std_logic is resolved std_ulogic;
 
   --  Vector of std_logic.
-  type std_logic_vector is array (natural range <>) of std_logic;
+  type std_logic_vector is array (natural range <>) of std_logic; --!V08
+  subtype std_logic_vector is (resolved) std_ulogic_vector;       --V08
 
   --  Subtypes of std_ulogic.  The names give the values.
   subtype X01   is resolved std_ulogic range 'X' to '1';
@@ -70,34 +69,75 @@ package std_logic_1164 is
   function "or"   (l : std_ulogic; r : std_ulogic) return UX01;
   function "nor"  (l : std_ulogic; r : std_ulogic) return UX01;
   function "xor"  (l : std_ulogic; r : std_ulogic) return UX01;
-  function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;
+  function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;  --!V87
   function "not"  (l : std_ulogic) return UX01;
 
   --  Logical operators for vectors.
   --  An assertion of severity failure fails if the length of L and R aren't
   --  equal.  The result range is 1 to L'Length.
-  function "and"  (l, r : std_logic_vector) return std_logic_vector;
-  function "nand" (l, r : std_logic_vector) return std_logic_vector;
-  function "or"   (l, r : std_logic_vector) return std_logic_vector;
-  function "nor"  (l, r : std_logic_vector) return std_logic_vector;
-  function "xor"  (l, r : std_logic_vector) return std_logic_vector;
-  function "xnor" (l, r : std_logic_vector) return std_logic_vector;
-  function "not"  (l : std_logic_vector) return std_logic_vector;
+  function "and"  (l, r : std_logic_vector) return std_logic_vector; --!V08
+  function "nand" (l, r : std_logic_vector) return std_logic_vector; --!V08
+  function "or"   (l, r : std_logic_vector) return std_logic_vector; --!V08
+  function "nor"  (l, r : std_logic_vector) return std_logic_vector; --!V08
+  function "xor"  (l, r : std_logic_vector) return std_logic_vector; --!V08
+  function "xnor" (l, r : std_logic_vector) return std_logic_vector; --V93
+  function "not"  (l : std_logic_vector) return std_logic_vector;    --!V08
 
   function "and"  (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "or"   (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "nor"  (l, r : std_ulogic_vector) return std_ulogic_vector;
   function "xor"  (l, r : std_ulogic_vector) return std_ulogic_vector;
-  function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
+  function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector; --!V87
   function "not"  (l : std_ulogic_vector) return std_ulogic_vector;
+                                                                  --V08
+  function "and"  (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "and"  (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+  function "nand" (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "nand" (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+  function "or"   (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "or"   (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+  function "nor"  (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "nor"  (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+  function "xor"  (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "xor"  (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+  function "xnor" (l : std_ulogic_vector; r : std_ulogic       )  --V08
+    return std_ulogic_vector;                                     --V08
+  function "xnor" (l : std_ulogic;        r : std_ulogic_vector)  --V08
+    return std_ulogic_vector;                                     --V08
+                                                                  --V08
+  function "and"  (l : std_ulogic_vector) return std_ulogic;      --V08
+  function "nand" (l : std_ulogic_vector) return std_ulogic;      --V08
+  function "or"   (l : std_ulogic_vector) return std_ulogic;      --V08
+  function "nor"  (l : std_ulogic_vector) return std_ulogic;      --V08
+  function "xor"  (l : std_ulogic_vector) return std_ulogic;      --V08
+  function "xnor" (l : std_ulogic_vector) return std_ulogic;      --V08
+                                                                  --V08
+  function "sll"  (l : std_ulogic_vector; r : integer)            --V08
+    return std_ulogic_vector;                                     --V08
+  function "srl"  (l : std_ulogic_vector; r : integer)            --V08
+    return std_ulogic_vector;                                     --V08
+  function "rol"  (l : std_ulogic_vector; r : integer)            --V08
+    return std_ulogic_vector;                                     --V08
+  function "ror"  (l : std_ulogic_vector; r : integer)            --V08
+    return std_ulogic_vector;                                     --V08
 
   --  Conversion functions.
   --  The result range (for vectors) is S'Length - 1 downto 0.
   --  XMAP is return for values not in '0', '1', 'L', 'H'.
   function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
-  function to_bitvector (s : std_logic_vector; xmap : bit := '0')
-    return bit_vector;
+  function to_bitvector (s : std_logic_vector; xmap : bit := '0')   --!V08
+    return bit_vector;                                              --!V08
   function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
     return bit_vector;
 
@@ -107,29 +147,65 @@ package std_logic_1164 is
   function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
   function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector;
 
+  alias to_bit_vector is                                              --V08
+    to_bitvector[std_ulogic_vector, bit return bit_vector];           --V08
+  alias to_bv is                                                      --V08
+    to_bitvector[std_ulogic_vector, bit return bit_vector];           --V08
+                                                                      --V08
+  alias to_std_logic_vector is                                        --V08
+    to_stdlogicvector[bit_vector return std_logic_vector];            --V08
+  alias to_slv is                                                     --V08
+    to_stdlogicvector[bit_vector return std_logic_vector];            --V08
+                                                                      --V08
+  alias to_std_logic_vector is                                        --V08
+    to_stdlogicvector[std_ulogic_vector return std_logic_vector];     --V08
+  alias to_slv is                                                     --V08
+    to_stdlogicvector[std_ulogic_vector return std_logic_vector];     --V08
+                                                                      --V08
+  alias to_std_ulogic_vector is                                       --V08
+    to_stdulogicvector[bit_vector return std_ulogic_vector];          --V08
+  alias to_sulv is                                                    --V08
+    to_stdulogicvector[bit_vector return std_ulogic_vector];          --V08
+                                                                      --V08
+  alias to_std_ulogic_vector is                                       --V08
+    to_stdulogicvector[std_logic_vector return std_ulogic_vector];    --V08
+  alias to_sulv is                                                    --V08
+    to_stdulogicvector[std_logic_vector return std_ulogic_vector];    --V08
+                                                                      --V08
   --  Normalization.
   --  The result range (for vectors) is 1 to S'Length.
-  function to_X01 (s : std_logic_vector) return std_logic_vector;
+  function to_01  (s : std_ulogic_vector; xmap : std_ulogic := '0')   --V08
+    return std_ulogic_vector;                                         --V08
+  function to_01  (s : std_ulogic;        xmap : std_ulogic := '0')   --V08
+    return std_ulogic;                                                --V08
+  function to_01  (s : bit_vector;        xmap : std_ulogic := '0')   --V08
+    return std_ulogic_vector;                                         --V08
+  function to_01  (s : bit;               xmap : std_ulogic := '0')   --V08
+    return std_ulogic;                                                --V08
+                                                                      --V08
+  function to_X01 (s : std_logic_vector) return std_logic_vector;     --!V08
   function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
   function to_X01 (s : std_ulogic) return X01;
-  function to_X01 (b : bit_vector) return std_logic_vector;
+  function to_X01 (b : bit_vector) return std_logic_vector;           --!V08
   function to_X01 (b : bit_vector) return std_ulogic_vector;
   function to_X01 (b : bit) return X01;
 
-  function to_X01Z (s : std_logic_vector) return std_logic_vector;
+  function to_X01Z (s : std_logic_vector) return std_logic_vector;    --!V08
   function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
   function to_X01Z (s : std_ulogic) return X01Z;
-  function to_X01Z (b : bit_vector) return std_logic_vector;
+  function to_X01Z (b : bit_vector) return std_logic_vector;          --!V08
   function to_X01Z (b : bit_vector) return std_ulogic_vector;
   function to_X01Z (b : bit) return X01Z;
 
-  function to_UX01 (s : std_logic_vector) return std_logic_vector;
+  function to_UX01 (s : std_logic_vector) return std_logic_vector;    --!V08
   function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
   function to_UX01 (s : std_ulogic) return UX01;
-  function to_UX01 (b : bit_vector) return std_logic_vector;
+  function to_UX01 (b : bit_vector) return std_logic_vector;          --!V08
   function to_UX01 (b : bit_vector) return std_ulogic_vector;
   function to_UX01 (b : bit) return UX01;
 
+  function "??" (l : std_ulogic) return boolean;                      --V08
+                                                                      --V08
   --  Edge detection.
   --  An edge is detected in case of event on s, and X01 normalized value
   --  rises from 0 to 1 or falls from 1 to 0.
@@ -138,6 +214,6 @@ package std_logic_1164 is
 
   --  Test for unknown.  Only 0, 1, L and H are known values.
   function is_X (s : std_ulogic_vector) return boolean;
-  function is_X (s : std_logic_vector) return boolean;
+  function is_X (s : std_logic_vector) return boolean;                --!V08
   function is_X (s : std_ulogic) return boolean;
 end std_logic_1164;