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authorUnai Martinez-Corral <38422348+umarcor@users.noreply.github.com>2021-07-02 00:10:18 +0100
committerGitHub <noreply@github.com>2021-07-02 00:10:18 +0100
commit1da694fe05363bf29359b5290042073774a11f25 (patch)
treeb4d55f210cfbf90847dc56a60058afa819107030 /pyGHDL/dom/Aggregates.py
parent69e6630acb723282ddde95ad0681ac71686df8e8 (diff)
parentae51fcf65f195e065987f379410d3f68c14f4a2b (diff)
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pyHDL: CLI Update for DOM (#1808)
Diffstat (limited to 'pyGHDL/dom/Aggregates.py')
-rw-r--r--pyGHDL/dom/Aggregates.py32
1 files changed, 8 insertions, 24 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 32dc1cacf..87bc44360 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -48,12 +48,11 @@ from pyVHDLModel.VHDLModel import (
NamedAggregateElement as VHDLModel_NamedAggregateElement,
OthersAggregateElement as VHDLModel_OthersAggregateElement,
Expression,
+ Symbol,
)
from pyGHDL.libghdl._types import Iir
from pyGHDL.dom import DOMMixin
from pyGHDL.dom.Range import Range
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol
-
__all__ = []
@@ -61,48 +60,33 @@ __all__ = []
@export
class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
def __init__(self, node: Iir, expression: Expression):
- super().__init__()
+ super().__init__(expression)
DOMMixin.__init__(self, node)
- self._expression = expression
-
@export
class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
def __init__(self, node: Iir, index: Expression, expression: Expression):
- super().__init__()
+ super().__init__(index, expression)
DOMMixin.__init__(self, node)
- self._index = index
- self._expression = expression
-
@export
class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
- def __init__(self, node: Iir, r: Range, expression: Expression):
- super().__init__()
+ def __init__(self, node: Iir, rng: Range, expression: Expression):
+ super().__init__(rng, expression)
DOMMixin.__init__(self, node)
- self._range = r
- self._expression = expression
-
@export
class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
- def __init__(
- self, node: Iir, name: EnumerationLiteralSymbol, expression: Expression
- ):
- super().__init__()
+ def __init__(self, node: Iir, name: Symbol, expression: Expression):
+ super().__init__(name, expression)
DOMMixin.__init__(self, node)
- self._name = name
- self._expression = expression
-
@export
class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
def __init__(self, node: Iir, expression: Expression):
- super().__init__()
+ super().__init__(expression)
DOMMixin.__init__(self, node)
-
- self._expression = expression