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authorumarcor <unai.martinezcorral@ehu.eus>2021-06-18 19:25:53 +0200
committerPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-06-19 15:25:07 +0200
commita81f2f777e30dadc775380a362c7fe38280a5234 (patch)
tree932d9722504f1884e07e86ecfd099da437b5be91 /pyGHDL/dom/Aggregates.py
parentbc693d0a5a725a2806656117d65b926150e71cb4 (diff)
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pyGHDL: run black
Diffstat (limited to 'pyGHDL/dom/Aggregates.py')
-rw-r--r--pyGHDL/dom/Aggregates.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 89acfa312..ac8ecbca8 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -48,14 +48,14 @@ from pyVHDLModel.VHDLModel import (
IndexedAggregateElement as VHDLModel_IndexedAggregateElement,
RangedAggregateElement as VHDLModel_RangedAggregateElement,
NamedAggregateElement as VHDLModel_NamedAggregateElement,
- OthersAggregateElement as VHDLModel_OthersAggregateElement, Expression
+ OthersAggregateElement as VHDLModel_OthersAggregateElement,
+ Expression,
)
__all__ = []
-
@export
class SimpleAggregateElement(VHDLModel_SimpleAggregateElement):
def __init__(self, expression: Expression):