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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-07-26 00:13:11 +0200 |
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committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:31 +0200 |
commit | ca39821dc013a877a8dbdfabbc3b861eb4d4d2e3 (patch) | |
tree | b731d3bddd9c8e3e7b288de088ad54510b6085ba /pyGHDL/dom/Aggregates.py | |
parent | 9df82e519d7e93168d43fb414c48c9e547b0c306 (diff) | |
download | ghdl-ca39821dc013a877a8dbdfabbc3b861eb4d4d2e3.tar.gz ghdl-ca39821dc013a877a8dbdfabbc3b861eb4d4d2e3.tar.bz2 ghdl-ca39821dc013a877a8dbdfabbc3b861eb4d4d2e3.zip |
Adjusted to renaming in pyVHDLModel.
Diffstat (limited to 'pyGHDL/dom/Aggregates.py')
-rw-r--r-- | pyGHDL/dom/Aggregates.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py index 87bc44360..6ca0734e7 100644 --- a/pyGHDL/dom/Aggregates.py +++ b/pyGHDL/dom/Aggregates.py @@ -9,7 +9,7 @@ # Authors: # Patrick Lehmann # -# Package module: DOM: VHDL design units (e.g. context or package). +# Package module: DOM: Aggregates. # # License: # ============================================================================ @@ -41,7 +41,7 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E """ from pydecor import export -from pyVHDLModel.VHDLModel import ( +from pyVHDLModel.SyntaxModel import ( SimpleAggregateElement as VHDLModel_SimpleAggregateElement, IndexedAggregateElement as VHDLModel_IndexedAggregateElement, RangedAggregateElement as VHDLModel_RangedAggregateElement, |