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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-23 09:02:47 +0200 |
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committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:37 +0200 |
commit | 8b98e2883b40b00922c9944c2470211ee055a9a5 (patch) | |
tree | 05a31686d247ef71cb512ac79643f3a309e72eeb /pyGHDL/dom/Expression.py | |
parent | 8fb4da723067b2ff99050f9ef9fc0bbd3c835ef4 (diff) | |
download | ghdl-8b98e2883b40b00922c9944c2470211ee055a9a5.tar.gz ghdl-8b98e2883b40b00922c9944c2470211ee055a9a5.tar.bz2 ghdl-8b98e2883b40b00922c9944c2470211ee055a9a5.zip |
Fixes due to a bug in pyVHDLModel. Name Context was used twice.
Diffstat (limited to 'pyGHDL/dom/Expression.py')
-rw-r--r-- | pyGHDL/dom/Expression.py | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 3769b9fb6..ce5945d46 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -83,7 +83,7 @@ from pyVHDLModel.SyntaxModel import ( SubtypeAllocation as VHDLModel_SubtypeAllocation, QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation, Aggregate as VHDLModel_Aggregate, - Expression, + ExpressionUnion, AggregateElement, SubtypeOrSymbol, Symbol, @@ -130,7 +130,7 @@ class _ParseBinaryExpressionMixin: class InverseExpression( VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin ): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -139,7 +139,7 @@ class InverseExpression( class IdentityExpression( VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin ): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -148,7 +148,7 @@ class IdentityExpression( class NegationExpression( VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin ): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -157,7 +157,7 @@ class NegationExpression( class AbsoluteExpression( VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin ): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -166,7 +166,7 @@ class AbsoluteExpression( class ParenthesisExpression( VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin ): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @@ -180,14 +180,14 @@ class ParenthesisExpression( @export class TypeConversion(VHDLModel_TypeConversion, DOMMixin): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__(operand) DOMMixin.__init__(self, node) @export class FunctionCall(VHDLModel_FunctionCall, DOMMixin): - def __init__(self, node: Iir, operand: Expression): + def __init__(self, node: Iir, operand: ExpressionUnion): super().__init__() DOMMixin.__init__(self, node) @@ -211,14 +211,14 @@ class RangeExpression(VHDLModel_RangeExpression, DOMMixin): @export class AscendingRangeExpression(VHDLModel_AscendingRangeExpression, DOMMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -227,7 +227,7 @@ class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin): class AdditionExpression( VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -236,7 +236,7 @@ class AdditionExpression( class SubtractionExpression( VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -245,7 +245,7 @@ class SubtractionExpression( class ConcatenationExpression( VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -254,7 +254,7 @@ class ConcatenationExpression( class MultiplyExpression( VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -263,7 +263,7 @@ class MultiplyExpression( class DivisionExpression( VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -272,7 +272,7 @@ class DivisionExpression( class RemainderExpression( VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -281,7 +281,7 @@ class RemainderExpression( class ModuloExpression( VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -290,56 +290,56 @@ class ModuloExpression( class ExponentiationExpression( VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressionMixin): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -348,7 +348,7 @@ class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressio class UnequalExpression( VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -357,7 +357,7 @@ class UnequalExpression( class LessThanExpression( VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -366,7 +366,7 @@ class LessThanExpression( class LessEqualExpression( VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -375,7 +375,7 @@ class LessEqualExpression( class GreaterThanExpression( VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -384,7 +384,7 @@ class GreaterThanExpression( class GreaterEqualExpression( VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -393,7 +393,7 @@ class GreaterEqualExpression( class MatchingEqualExpression( VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -402,7 +402,7 @@ class MatchingEqualExpression( class MatchingUnequalExpression( VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -411,7 +411,7 @@ class MatchingUnequalExpression( class MatchingLessThanExpression( VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -420,7 +420,7 @@ class MatchingLessThanExpression( class MatchingLessEqualExpression( VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -429,7 +429,7 @@ class MatchingLessEqualExpression( class MatchingGreaterThanExpression( VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -438,7 +438,7 @@ class MatchingGreaterThanExpression( class MatchingGreaterEqualExpression( VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -447,7 +447,7 @@ class MatchingGreaterEqualExpression( class ShiftRightLogicExpression( VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -456,7 +456,7 @@ class ShiftRightLogicExpression( class ShiftLeftLogicExpression( VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -465,7 +465,7 @@ class ShiftLeftLogicExpression( class ShiftRightArithmeticExpression( VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -474,7 +474,7 @@ class ShiftRightArithmeticExpression( class ShiftLeftArithmeticExpression( VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -483,7 +483,7 @@ class ShiftLeftArithmeticExpression( class RotateRightExpression( VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @@ -492,14 +492,14 @@ class RotateRightExpression( class RotateLeftExpression( VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin ): - def __init__(self, node: Iir, left: Expression, right: Expression): + def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion): super().__init__(left, right) DOMMixin.__init__(self, node) @export class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin): - def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: Expression): + def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: ExpressionUnion): super().__init__(subtype, operand) DOMMixin.__init__(self, node) |