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authorPatrick Lehmann <Paebbels@gmail.com>2023-01-12 05:53:48 +0100
committerGitHub <noreply@github.com>2023-01-12 05:53:48 +0100
commitfb7ef864c019d325f3fc37125e6d6cdc50ae4b83 (patch)
tree8ecca65254f939c987f182531b0cc7e13ff422b3 /pyGHDL/dom/Expression.py
parent60774db2a547493b7f89de6239794b7354a0e31f (diff)
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Dependency Graphs (#2308)
* Further fixes to the example code. * Bumped dependencies. * Fixed Debouncer example code. * Some more cleanup. * Black's opinion. * Run with pyVHDLModel dev-branch. * Fixed imports for Name. * Fixed test case. * Added a formatter to write dependency graphs and hierarchy as graphml. * Improved GraphML formatting. * Write compile order graph. * Computing compile order. * Bumped dependencies. * Black's opinion. * Fixed incorrect dependency.
Diffstat (limited to 'pyGHDL/dom/Expression.py')
-rw-r--r--pyGHDL/dom/Expression.py31
1 files changed, 15 insertions, 16 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 81ecfa380..608801af6 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -34,17 +34,17 @@ from typing import List, Union
from pyTooling.Decorators import export
-from pyVHDLModel.SyntaxModel import (
+from pyVHDLModel.Base import ExpressionUnion
+from pyVHDLModel.Symbol import Symbol
+from pyVHDLModel.Expression import (
UnaryExpression as VHDLModel_UnaryExpression,
- BinaryExpression as VHDLModel_BinaryExpression,
- InverseExpression as VHDLModel_InverseExpression,
- IdentityExpression as VHDLModel_IdentityExpression,
NegationExpression as VHDLModel_NegationExpression,
+ IdentityExpression as VHDLModel_IdentityExpression,
+ InverseExpression as VHDLModel_InverseExpression,
AbsoluteExpression as VHDLModel_AbsoluteExpression,
- SubExpression as VHDLModel_ParenthesisExpression,
TypeConversion as VHDLModel_TypeConversion,
- FunctionCall as VHDLModel_FunctionCall,
- QualifiedExpression as VHDLModel_QualifiedExpression,
+ SubExpression as VHDLModel_ParenthesisExpression,
+ BinaryExpression as VHDLModel_BinaryExpression,
RangeExpression as VHDLModel_RangeExpression,
AscendingRangeExpression as VHDLModel_AscendingRangeExpression,
DescendingRangeExpression as VHDLModel_DescendingRangeExpression,
@@ -64,29 +64,28 @@ from pyVHDLModel.SyntaxModel import (
XnorExpression as VHDLModel_XnorExpression,
EqualExpression as VHDLModel_EqualExpression,
UnequalExpression as VHDLModel_UnequalExpression,
- LessThanExpression as VHDLModel_LessThanExpression,
- LessEqualExpression as VHDLModel_LessEqualExpression,
GreaterThanExpression as VHDLModel_GreaterThanExpression,
GreaterEqualExpression as VHDLModel_GreaterEqualExpression,
+ LessThanExpression as VHDLModel_LessThanExpression,
+ LessEqualExpression as VHDLModel_LessEqualExpression,
MatchingEqualExpression as VHDLModel_MatchingEqualExpression,
MatchingUnequalExpression as VHDLModel_MatchingUnequalExpression,
- MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
- MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
MatchingGreaterThanExpression as VHDLModel_MatchingGreaterThanExpression,
MatchingGreaterEqualExpression as VHDLModel_MatchingGreaterEqualExpression,
+ MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
+ MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression,
ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression,
ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression,
ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression,
RotateRightExpression as VHDLModel_RotateRightExpression,
RotateLeftExpression as VHDLModel_RotateLeftExpression,
+ QualifiedExpression as VHDLModel_QualifiedExpression,
+ FunctionCall as VHDLModel_FunctionCall,
SubtypeAllocation as VHDLModel_SubtypeAllocation,
QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation,
- Aggregate as VHDLModel_Aggregate,
- ExpressionUnion,
AggregateElement,
- SubtypeOrSymbol,
- Symbol,
+ Aggregate as VHDLModel_Aggregate,
)
from pyGHDL.libghdl import utils
@@ -434,7 +433,7 @@ class RotateLeftExpression(VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinar
@export
class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin):
- def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: ExpressionUnion):
+ def __init__(self, node: Iir, subtype: Symbol, operand: ExpressionUnion):
super().__init__(subtype, operand)
DOMMixin.__init__(self, node)