pyGHDL: update to pyVHDLModel v0.11.5 (#1822)

New Features:

* Handle multiple identifiers in generics, ports, parameters and objects.
* `ghdl-dom` now also accepts `-D` for directories to scan.
* Resolve architectures to entities.
* Context reference
* Library clause
* Use clause
* Handle contexts of design units
* New `OpenName`
* Translate concurrent statements:
  * Component instantiation
  * Entity instantiation
  * Configuration instantiation
  * If..generate statement
  * Case..generate statement
  * For..generate statement
  * Block statement
  * Process statement
  * Concurrent simple signal assignment
  * Concurrent procedure call
* Translate sequential statements:
  * If statement
  * Case statement
  * For loop
  * Sequential simple signal assignment
  * Sequential procedure call
  * Sequential assert statement
  * Sequential report statement
  * Wait statement
* Print hierarchy in pretty-print
* New binding to `str_table` `string8_address`

Changes:

* Adjusted to renaming of `pyVHDLModel.VHDLModel` to `pyVHDLModel.SyntaxModel`.
* Adjust DOM to a change in pyVHDLModel: some Identifiers being now a list of identifiers.
* Reordered items in GHA workflow `Test.yml`.
* Improved ranges

Bug fixes:

* Fixed typo in IIR translation of `Greater_Than_Or_Equal_Operator`: should be `GreaterEqualExpression`.
* Wrap type marks in a `SimpleName`.
* Fixed syntax of lists in GHA workflow `Test.yml`.
* Fixed handling of bit-string literals.

1 files changed, 10 insertions, 6 deletions

diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 784039d45..26be52ec8 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: Literals.
 #
 # License:
 # ============================================================================
@@ -32,7 +32,7 @@
 # ============================================================================
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     NullLiteral as VHDLModel_NullLiteral,
     EnumerationLiteral as VHDLModel_EnumerationLiteral,
     IntegerLiteral as VHDLModel_IntegerLiteral,
@@ -42,7 +42,7 @@ from pyVHDLModel.VHDLModel import (
     CharacterLiteral as VHDLModel_CharacterLiteral,
     StringLiteral as VHDLModel_StringLiteral,
 )
-from pyGHDL.libghdl import name_table
+from pyGHDL.libghdl import name_table, str_table
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin
@@ -149,6 +149,10 @@ class StringLiteral(VHDLModel_StringLiteral, DOMMixin):
 
     @classmethod
     def parse(cls, literalNode: Iir) -> "StringLiteral":
-        stringID = nodes.Get_String8_Id(literalNode)
-        value = name_table.Get_Name_Ptr(stringID)
-        return cls(literalNode, value)
+        if nodes.Get_Bit_String_Base(literalNode) is nodes.NumberBaseType.Base_None:
+            value = str_table.Get_String8_Ptr(
+                nodes.Get_String8_Id(literalNode), nodes.Get_String_Length(literalNode)
+            )
+            return cls(literalNode, value)
+        else:
+            print("[NOT IMPLEMENTED] Bit String Literal not supported yet")