pyGHDL: update to pyVHDLModel v0.11.5 (#1822)

New Features:

* Handle multiple identifiers in generics, ports, parameters and objects.
* `ghdl-dom` now also accepts `-D` for directories to scan.
* Resolve architectures to entities.
* Context reference
* Library clause
* Use clause
* Handle contexts of design units
* New `OpenName`
* Translate concurrent statements:
  * Component instantiation
  * Entity instantiation
  * Configuration instantiation
  * If..generate statement
  * Case..generate statement
  * For..generate statement
  * Block statement
  * Process statement
  * Concurrent simple signal assignment
  * Concurrent procedure call
* Translate sequential statements:
  * If statement
  * Case statement
  * For loop
  * Sequential simple signal assignment
  * Sequential procedure call
  * Sequential assert statement
  * Sequential report statement
  * Wait statement
* Print hierarchy in pretty-print
* New binding to `str_table` `string8_address`

Changes:

* Adjusted to renaming of `pyVHDLModel.VHDLModel` to `pyVHDLModel.SyntaxModel`.
* Adjust DOM to a change in pyVHDLModel: some Identifiers being now a list of identifiers.
* Reordered items in GHA workflow `Test.yml`.
* Improved ranges

Bug fixes:

* Fixed typo in IIR translation of `Greater_Than_Or_Equal_Operator`: should be `GreaterEqualExpression`.
* Wrap type marks in a `SimpleName`.
* Fixed syntax of lists in GHA workflow `Test.yml`.
* Fixed handling of bit-string literals.

1 files changed, 10 insertions, 2 deletions

diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py
index e09294d40..acb9cd1d6 100644
--- a/pyGHDL/dom/Names.py
+++ b/pyGHDL/dom/Names.py
@@ -32,10 +32,9 @@
 # ============================================================================
 from typing import List
 
-from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     SimpleName as VHDLModel_SimpleName,
     ParenthesisName as VHDLModel_ParenthesisName,
     IndexedName as VHDLModel_IndexedName,
@@ -43,8 +42,10 @@ from pyVHDLModel.VHDLModel import (
     SelectedName as VHDLModel_SelectedName,
     AttributeName as VHDLModel_AttributeName,
     AllName as VHDLModel_AllName,
+    OpenName as VHDLModel_OpenName,
     Name,
 )
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 
 __all__ = []
@@ -97,3 +98,10 @@ class AllName(VHDLModel_AllName, DOMMixin):
     def __init__(self, node: Iir, prefix: Name):
         super().__init__(prefix)
         DOMMixin.__init__(self, node)
+
+
+@export
+class OpenName(VHDLModel_OpenName, DOMMixin):
+    def __init__(self, node: Iir):
+        super().__init__()
+        DOMMixin.__init__(self, node)