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authorUnai Martinez-Corral <38422348+umarcor@users.noreply.github.com>2021-07-02 00:10:18 +0100
committerGitHub <noreply@github.com>2021-07-02 00:10:18 +0100
commit1da694fe05363bf29359b5290042073774a11f25 (patch)
treeb4d55f210cfbf90847dc56a60058afa819107030 /pyGHDL/dom/NonStandard.py
parent69e6630acb723282ddde95ad0681ac71686df8e8 (diff)
parentae51fcf65f195e065987f379410d3f68c14f4a2b (diff)
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pyHDL: CLI Update for DOM (#1808)
Diffstat (limited to 'pyGHDL/dom/NonStandard.py')
-rw-r--r--pyGHDL/dom/NonStandard.py13
1 files changed, 13 insertions, 0 deletions
diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py
index 1524b549f..bf48db900 100644
--- a/pyGHDL/dom/NonStandard.py
+++ b/pyGHDL/dom/NonStandard.py
@@ -42,6 +42,7 @@ from typing import Any
from pydecor import export
+from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
from pyVHDLModel.VHDLModel import (
Design as VHDLModel_Design,
Library as VHDLModel_Library,
@@ -198,6 +199,18 @@ class Document(VHDLModel_Document):
configuration = Configuration.parse(libraryUnit)
self.Configurations.append(configuration)
+ elif nodeKind == nodes.Iir_Kind.Vunit_Declaration:
+ vunit = VerificationUnit.parse(libraryUnit)
+ self.VerificationUnits.append(vunit)
+
+ elif nodeKind == nodes.Iir_Kind.Vprop_Declaration:
+ vprop = VerificationProperty.parse(libraryUnit)
+ self.VerificationProperties.append(vprop)
+
+ elif nodeKind == nodes.Iir_Kind.Vmode_Declaration:
+ vmod = VerificationMode.parse(libraryUnit)
+ self.VerificationModes.append(vmod)
+
else:
raise DOMException(
"Unknown design unit kind '{kindName}'({kind}).".format(