Added package declarations inside of declarations.

Added PSL Default clock (dummy).
Added Disconnect specification (dummy).

1 files changed, 21 insertions, 0 deletions

diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
index dd859e5b3..6c4ba76b3 100644
--- a/pyGHDL/dom/PSL.py
+++ b/pyGHDL/dom/PSL.py
@@ -39,12 +39,14 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 
 
 """
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.PSLModel import (
     VerificationUnit as VHDLModel_VerificationUnit,
     VerificationProperty as VHDLModel_VerificationProperty,
     VerificationMode as VHDLModel_VerificationMode,
+    DefaultClock as VHDLModel_DefaultClock,
 )
 
 from pyGHDL.libghdl._types import Iir
@@ -110,3 +112,22 @@ class VerificationMode(VHDLModel_VerificationMode, DOMMixin):
         # FIXME: needs an implementation
 
         return cls(vmodeNode, name)
+
+
+@export
+class DefaultClock(VHDLModel_DefaultClock, DOMMixin):
+    def __init__(
+        self,
+        node: Iir,
+        identifier: str,
+    ):
+        super().__init__(identifier)
+        DOMMixin.__init__(self, node)
+
+    @classmethod
+    def parse(cls, defaultClockNode: Iir):
+        name = GetNameOfNode(defaultClockNode)
+
+        # FIXME: needs an implementation
+
+        return cls(defaultClockNode, name)