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authorTristan Gingold <tgingold@free.fr>2019-10-11 06:21:24 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-11 06:21:24 +0200
commit2714a30c3753c76cda95eb994851a8be95e60ad9 (patch)
treeed759d92892d21a21cc5e60e2995e9feef5ed1a2 /python/libghdl/thin/vhdl/nodes.py
parentf4be996776af67b5242e9ec5fc18ec1fe27d0efb (diff)
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vhdl: recognize minus from std_logic_unsigned
Diffstat (limited to 'python/libghdl/thin/vhdl/nodes.py')
-rw-r--r--python/libghdl/thin/vhdl/nodes.py49
1 files changed, 27 insertions, 22 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 08feba5fc..d684700a6 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1176,28 +1176,33 @@ class Iir_Predefined:
Ieee_Std_Logic_Unsigned_Add_Int_Slv = 297
Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 298
Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 299
- Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 300
- Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 301
- Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 302
- Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 303
- Ieee_Std_Logic_Unsigned_Le_Slv_Int = 304
- Ieee_Std_Logic_Unsigned_Le_Int_Slv = 305
- Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 306
- Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 307
- Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 308
- Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 309
- Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 310
- Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 311
- Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 312
- Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 313
- Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 314
- Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 315
- Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 316
- Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 317
- Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 318
- Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 319
- Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 320
- Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 321
+ Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 300
+ Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 301
+ Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 302
+ Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 303
+ Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 304
+ Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 305
+ Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 306
+ Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 307
+ Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 308
+ Ieee_Std_Logic_Unsigned_Le_Slv_Int = 309
+ Ieee_Std_Logic_Unsigned_Le_Int_Slv = 310
+ Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 311
+ Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 312
+ Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 313
+ Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 314
+ Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 315
+ Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 316
+ Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 317
+ Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 318
+ Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 319
+ Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320
+ Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321
+ Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322
+ Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 323
+ Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 324
+ Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 325
+ Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 326
Get_Kind = libghdl.vhdl__nodes__get_kind
Get_Location = libghdl.vhdl__nodes__get_location