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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-30 03:54:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-30 03:54:04 +0200 |
| commit | ef80528ce62cfe8d17723f8142118057da8ad369 (patch) | |
| tree | 0716e1b5b25081a4229f087ac9500c1d49438435 /python/libghdl/thin/vhdl/nodes.py | |
| parent | 18ae5082cbae9ebc652455419b60a9d420281688 (diff) | |
| download | ghdl-ef80528ce62cfe8d17723f8142118057da8ad369.tar.gz ghdl-ef80528ce62cfe8d17723f8142118057da8ad369.tar.bz2 ghdl-ef80528ce62cfe8d17723f8142118057da8ad369.zip | |
vhdl: recognize ieee.numeric_std std_match.
Diffstat (limited to 'python/libghdl/thin/vhdl/nodes.py')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 55 |
1 files changed, 30 insertions, 25 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index cfe654030..8b99eefc4 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1135,31 +1135,36 @@ class Iir_Predefined: Ieee_Numeric_Std_Xnor_Sgn_Sgn = 260 Ieee_Numeric_Std_Neg_Uns = 261 Ieee_Numeric_Std_Neg_Sgn = 262 - Ieee_Math_Real_Ceil = 263 - Ieee_Math_Real_Log2 = 264 - Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 265 - Ieee_Std_Logic_Unsigned_Add_Slv_Int = 266 - Ieee_Std_Logic_Unsigned_Add_Int_Slv = 267 - Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 268 - Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 269 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 270 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 271 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 272 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 273 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 274 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 275 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 276 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 277 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 278 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 279 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 280 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 281 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 282 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 283 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 284 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 285 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 286 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 287 + Ieee_Numeric_Std_Match_Log = 263 + Ieee_Numeric_Std_Match_Uns = 264 + Ieee_Numeric_Std_Match_Sgn = 265 + Ieee_Numeric_Std_Match_Slv = 266 + Ieee_Numeric_Std_Match_Suv = 267 + Ieee_Math_Real_Ceil = 268 + Ieee_Math_Real_Log2 = 269 + Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 270 + Ieee_Std_Logic_Unsigned_Add_Slv_Int = 271 + Ieee_Std_Logic_Unsigned_Add_Int_Slv = 272 + Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 273 + Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 274 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 275 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 276 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 277 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 278 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 279 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 280 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 281 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 282 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 283 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 284 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 285 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 286 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 287 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 288 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 289 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 290 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 291 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 292 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |