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authorTristan Gingold <tgingold@free.fr>2020-06-12 07:47:46 +0200
committerTristan Gingold <tgingold@free.fr>2020-06-12 07:47:46 +0200
commitdb9c1fd3700995155b2d8a32d929b3d0dc9689e2 (patch)
treedf1d9c6510ba70e6c755f6428c6b902c40fe7b1a /python/libghdl
parent967047f328ba8e5a2172ab24200dc6481aa48927 (diff)
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vhdl: analyze and synth concurrent statements in vunit. Fix #1366
Diffstat (limited to 'python/libghdl')
-rw-r--r--python/libghdl/thin/vhdl/nodes.py5
1 files changed, 5 insertions, 0 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 04aa11dcb..e25d2ef95 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -496,6 +496,11 @@ class Iir_Kinds:
Iir_Kind.Psl_Rose,
Iir_Kind.Psl_Fell]
+ Generate_Statement = [
+ Iir_Kind.If_Generate_Statement,
+ Iir_Kind.Case_Generate_Statement,
+ Iir_Kind.For_Generate_Statement]
+
Composite_Subtype_Definition = [
Iir_Kind.Array_Subtype_Definition,
Iir_Kind.Record_Subtype_Definition]