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authorTristan Gingold <tgingold@free.fr>2019-06-29 03:58:07 +0200
committerTristan Gingold <tgingold@free.fr>2019-06-29 03:58:07 +0200
commit655866865db5d5c259a87105807dc7aed0d857d7 (patch)
treed768b2dd9601fe366ecaa5989f8545a9afd43290 /src/ghdldrv/ghdlsimul.adb
parente11afef1e7ffbf22bf0aaac0a7166b0aeee9fd2f (diff)
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vhdl: move annotations from simul to vhdl.
Diffstat (limited to 'src/ghdldrv/ghdlsimul.adb')
-rw-r--r--src/ghdldrv/ghdlsimul.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 52408b067..97adef30d 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -27,7 +27,7 @@ with Flags;
with Vhdl.Std_Package;
with Vhdl.Canon;
with Vhdl.Configuration;
-with Simul.Annotations;
+with Vhdl.Annotations;
with Simul.Elaboration;
with Simul.Simulation.Main;
with Simul.Debugger;
@@ -67,9 +67,9 @@ package body Ghdlsimul is
Common_Compile_Elab (Cmd_Name, Args, Opt_Arg, Top_Conf);
-- Annotate all units.
- Simul.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
+ Vhdl.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
for I in Design_Units.First .. Design_Units.Last loop
- Simul.Annotations.Annotate (Design_Units.Table (I));
+ Vhdl.Annotations.Annotate (Design_Units.Table (I));
end loop;
end Compile_Elab;