vhdl: move std_standard package to vhdl child.

4 files changed, 13 insertions, 13 deletions

diff --git a/src/ghdldrv/ghdlcomp.adb b/src/ghdldrv/ghdlcomp.adb
index 2ac085d9c..542042819 100644
--- a/src/ghdldrv/ghdlcomp.adb
+++ b/src/ghdldrv/ghdlcomp.adb
@@ -29,7 +29,7 @@ with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Name_Table;
 with Errorout; use Errorout;
 with Libraries;
-with Std_Package;
+with Vhdl.Std_Package;
 with Files_Map;
 with Version;
 
@@ -682,7 +682,7 @@ package body Ghdlcomp is
       while Is_Valid (It) loop
          File := Get_Element (It);
 
-         if File = Std_Package.Std_Standard_File then
+         if File = Vhdl.Std_Package.Std_Standard_File then
             null;
          elsif Source_File_Modified (File)
            or else Is_File_Outdated (File)
@@ -778,7 +778,7 @@ package body Ghdlcomp is
 
    function Is_Makeable_File (File : Iir_Design_File) return Boolean is
    begin
-      if File = Std_Package.Std_Standard_File then
+      if File = Vhdl.Std_Package.Std_Standard_File then
          return False;
       end if;
       return True;
diff --git a/src/ghdldrv/ghdllocal.adb b/src/ghdldrv/ghdllocal.adb
index a400ff69d..8b261279b 100644
--- a/src/ghdldrv/ghdllocal.adb
+++ b/src/ghdldrv/ghdllocal.adb
@@ -21,7 +21,7 @@ with GNAT.Directory_Operations;
 with Types; use Types;
 with Libraries;
 with Vhdl.Sem_Lib;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags;
 with Name_Table;
 with Std_Names;
@@ -1116,7 +1116,7 @@ package body Ghdllocal is
       end if;
       Flags.Bootstrap := True;
       Libraries.Load_Std_Library;
-      Vhdl.Disp_Vhdl.Disp_Vhdl (Std_Package.Std_Standard_Unit);
+      Vhdl.Disp_Vhdl.Disp_Vhdl (Vhdl.Std_Package.Std_Standard_Unit);
    end Perform_Action;
 
    --  Command --find-top.
@@ -1527,7 +1527,7 @@ package body Ghdllocal is
                         return True;
                      end if;
                      Dep_File := Get_Design_File (Dep);
-                     if Dep /= Std_Package.Std_Standard_Unit
+                     if Dep /= Vhdl.Std_Package.Std_Standard_Unit
                        and then
                        Files_Map.Is_Gt (Get_Analysis_Time_Stamp (Dep_File),
                                         Stamp)
diff --git a/src/ghdldrv/ghdlrun.adb b/src/ghdldrv/ghdlrun.adb
index 6763498f7..f8b3adaaf 100644
--- a/src/ghdldrv/ghdlrun.adb
+++ b/src/ghdldrv/ghdlrun.adb
@@ -32,7 +32,7 @@ with Ortho_Jit;
 with Ortho_Nodes; use Ortho_Nodes;
 with Trans_Decls;
 with Iirs; use Iirs;
-with Std_Package;
+with Vhdl.Std_Package;
 with Flags;
 with Errorout; use Errorout;
 with Libraries;
@@ -128,7 +128,7 @@ package body Ghdlrun is
       end if;
 
       if Time_Resolution /= 'a' then
-         Std_Package.Set_Time_Resolution (Time_Resolution);
+         Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
       end if;
 
       if Analyze_Only then
@@ -173,7 +173,7 @@ package body Ghdlrun is
       end if;
 
       if Time_Resolution = 'a' then
-         Time_Resolution := Std_Package.Get_Minimal_Time_Resolution;
+         Time_Resolution := Vhdl.Std_Package.Get_Minimal_Time_Resolution;
          if Time_Resolution = '?' then
             Time_Resolution := 'f';
          end if;
@@ -195,7 +195,7 @@ package body Ghdlrun is
             end;
          end if;
       end if;
-      Std_Package.Set_Time_Resolution (Time_Resolution);
+      Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
 
       --  Overwrite time resolution in flag string.
       Flags.Flag_String (5) := Time_Resolution;
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index cc968048f..b465ed8cc 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -26,7 +26,7 @@ with Types;
 with Flags;
 with Name_Table;
 with Errorout; use Errorout;
-with Std_Package;
+with Vhdl.Std_Package;
 with Libraries;
 with Vhdl.Canon;
 with Vhdl.Configuration;
@@ -61,14 +61,14 @@ package body Ghdlsimul is
       end if;
 
       if Time_Resolution /= 'a' then
-         Std_Package.Set_Time_Resolution (Time_Resolution);
+         Vhdl.Std_Package.Set_Time_Resolution (Time_Resolution);
       end if;
 
       if Analyze_Only then
          return;
       end if;
 
-      Simul.Annotations.Annotate (Std_Package.Std_Standard_Unit);
+      Simul.Annotations.Annotate (Vhdl.Std_Package.Std_Standard_Unit);
 
       Vhdl.Canon.Canon_Flag_Add_Labels := True;
       Vhdl.Canon.Canon_Flag_Sequentials_Stmts := True;