vhdl08: add support of case-generate statement

1 files changed, 5 insertions, 4 deletions

diff --git a/src/grt/grt-rtis_addr.adb b/src/grt/grt-rtis_addr.adb
index f8a35bd1f..8be2a2e75 100644
--- a/src/grt/grt-rtis_addr.adb
+++ b/src/grt/grt-rtis_addr.adb
@@ -135,10 +135,11 @@ package body Grt.Rtis_Addr is
       end if;
    end Get_Instance_Link;
 
-   function Get_If_Generate_Child (Ctxt : Rti_Context; Gen : Ghdl_Rti_Access)
-                                  return Rti_Context
+   function Get_If_Case_Generate_Child
+     (Ctxt : Rti_Context; Gen : Ghdl_Rti_Access) return Rti_Context
    is
-      pragma Assert (Gen.Kind = Ghdl_Rtik_If_Generate);
+      pragma Assert (Gen.Kind = Ghdl_Rtik_If_Generate
+                       or Gen.Kind = Ghdl_Rtik_Case_Generate);
       Blk : constant Ghdl_Rtin_Block_Acc := To_Ghdl_Rtin_Block_Acc (Gen);
       Base_Addr : constant Address := Ctxt.Base + Blk.Loc;
 
@@ -152,7 +153,7 @@ package body Grt.Rtis_Addr is
    begin
       return (Base => To_Addr_Acc (Base_Addr).all,
               Block => Blk.Children (Id));
-   end Get_If_Generate_Child;
+   end Get_If_Case_Generate_Child;
 
    function Loc_To_Addr (Depth : Ghdl_Rti_Depth;
                          Loc : Ghdl_Rti_Loc;