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author | Ben Reynwar <ben@reynwar.net> | 2020-05-10 07:56:48 -0700 |
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committer | GitHub <noreply@github.com> | 2020-05-10 16:56:48 +0200 |
commit | a0919fe84b25f37d0307805650379830094fcfbf (patch) | |
tree | 01d1e5693e7ce954495eca1473319a32057c57fe /src/grt/grt-vpi.adb | |
parent | 06202188e0e88c0096518415413c08bd0471644b (diff) | |
download | ghdl-a0919fe84b25f37d0307805650379830094fcfbf.tar.gz ghdl-a0919fe84b25f37d0307805650379830094fcfbf.tar.bz2 ghdl-a0919fe84b25f37d0307805650379830094fcfbf.zip |
Constants in vpi (#1297)
* Adding some very basic vpi tests.
* Modify test so that's it's checking VPI access to constants.
* Provide VPI to access constants.
* Add vpi tests to testsuite.
* Fix bug to allow getting values of generic/constant boolean and std_logic.
* Fix stupid copying mistake in last commit.
* Formatting and trying to get tests working on windows.
* Fixing comment and removing redundant VhpiConstantDeclK
Diffstat (limited to 'src/grt/grt-vpi.adb')
-rw-r--r-- | src/grt/grt-vpi.adb | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb index a2884bd76..afcc2692f 100644 --- a/src/grt/grt-vpi.adb +++ b/src/grt/grt-vpi.adb @@ -574,6 +574,15 @@ package body Grt.Vpi is return vpiParameter; end if; end; + when VhpiConstDeclK => + declare + Info : Verilog_Wire_Info; + begin + Get_Verilog_Wire (Res, Info); + if Info.Vtype /= Vcd_Bad then + return vpiConstant; + end if; + end; when others => null; end case; @@ -596,6 +605,9 @@ package body Grt.Vpi is when vpiParameter => return new struct_vpiHandle'(mType => vpiParameter, Ref => Res); + when vpiConstant => + return new struct_vpiHandle'(mType => vpiConstant, + Ref => Res); when others => return null; end case; @@ -859,7 +871,8 @@ package body Grt.Vpi is case Vhpi_Get_Kind (Obj) is when VhpiPortDeclK | VhpiSigDeclK - | VhpiGenericDeclK => + | VhpiGenericDeclK + | VhpiConstDeclK => null; when others => return null; @@ -894,13 +907,15 @@ package body Grt.Vpi is Append_Bin (Ghdl_U64 (V), 32); end; when Vcd_Bit - | Vcd_Bool - | Vcd_Bitvector => + | Vcd_Bool => + Append (Buf_Value, Map_Std_B1 (Verilog_Wire_Val (Info).B1)); + when Vcd_Bitvector => for J in 0 .. Len - 1 loop Append (Buf_Value, Map_Std_B1 (Verilog_Wire_Val (Info, J).B1)); end loop; - when Vcd_Stdlogic - | Vcd_Stdlogic_Vector => + when Vcd_Stdlogic => + Append (Buf_Value, E8_To_Char (Verilog_Wire_Val (Info).E8)); + when Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop Append (Buf_Value, E8_To_Char (Verilog_Wire_Val (Info, J).E8)); end loop; |