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| author | Tristan Gingold <tgingold@free.fr> | 2016-03-22 05:34:06 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-03-22 05:44:49 +0100 |
| commit | db9df06f901abe21976ae8f5d3b680965daef70b (patch) | |
| tree | 7a5a5d9a2485c9fb0b593dd1f25f5b96defbbb34 /src/psl/psl-rewrites.adb | |
| parent | 89cff67d5cf64c46818043e269c1d9f56a2ac149 (diff) | |
| download | ghdl-db9df06f901abe21976ae8f5d3b680965daef70b.tar.gz ghdl-db9df06f901abe21976ae8f5d3b680965daef70b.tar.bz2 ghdl-db9df06f901abe21976ae8f5d3b680965daef70b.zip | |
PSL: add clocked SERE, make endpoints visible from VHDL.
Diffstat (limited to 'src/psl/psl-rewrites.adb')
| -rw-r--r-- | src/psl/psl-rewrites.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/psl/psl-rewrites.adb b/src/psl/psl-rewrites.adb index 173f4da94..de88939de 100644 --- a/src/psl/psl-rewrites.adb +++ b/src/psl/psl-rewrites.adb @@ -294,6 +294,10 @@ package body PSL.Rewrites is return Rewrite_Equal_Repeat_Seq (N); when N_Braced_SERE => return Rewrite_SERE (Get_SERE (N)); + when N_Clocked_SERE => + Set_SERE (N, Rewrite_SERE (Get_SERE (N))); + Set_Boolean (N, Rewrite_Boolean (Get_Boolean (N))); + return N; when N_Within_SERE => Set_Left (N, Rewrite_SERE (Get_Left (N))); Set_Right (N, Rewrite_SERE (Get_Right (N))); |