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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-30 18:59:31 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-30 19:17:28 +0100 |
| commit | 4863badab145faf21f31a76997c7bb7274320502 (patch) | |
| tree | 12e4d33e4346a534d4bc58edcd2c90c7b082d355 /src/simul/simul-vhdl_elab.adb | |
| parent | 75fa271425d1be151bb451c1b14539cc4dc428ed (diff) | |
| download | ghdl-4863badab145faf21f31a76997c7bb7274320502.tar.gz ghdl-4863badab145faf21f31a76997c7bb7274320502.tar.bz2 ghdl-4863badab145faf21f31a76997c7bb7274320502.zip | |
simul: use same packing order for nets and for values.
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 8e2db63ad..49b24b42b 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -104,7 +104,7 @@ package body Simul.Vhdl_Elab is end if; for I in 1 .. Len loop Mark_Resolved_Signals - (Sig_Off + (Len - I) * Typ.Arr_El.W, + (Sig_Off + (I - 1) * Typ.Arr_El.W, El_Type, Typ.Arr_El, Vec, Already_Resolved); end loop; |