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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-02 19:40:11 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-03 16:47:25 +0100 |
| commit | 5fbe7eadaeb56ca29553c0cf6564a2151da5b423 (patch) | |
| tree | 8ee1c81f42bac866dd064c69683a15af34e3abcc /src/simul | |
| parent | 131063995d1065a78858feb8afbb0d694ea827b4 (diff) | |
| download | ghdl-5fbe7eadaeb56ca29553c0cf6564a2151da5b423.tar.gz ghdl-5fbe7eadaeb56ca29553c0cf6564a2151da5b423.tar.bz2 ghdl-5fbe7eadaeb56ca29553c0cf6564a2151da5b423.zip | |
simul: skip psl default clock in declarations
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index fed1c7d74..229c75c77 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -439,6 +439,7 @@ package body Simul.Vhdl_Elab is | Iir_Kind_Component_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Protected_Type_Body + | Iir_Kind_Psl_Default_Clock | Iir_Kind_Use_Clause | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration => |