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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-01 18:38:12 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-01 18:38:12 +0100 |
| commit | ddf587a71472a8740b044c976b8f67c537ab0c06 (patch) | |
| tree | 19c1fec5c60ce941ff427eae6805a83b144bbbdb /src/simul | |
| parent | 4ac2b03fb79b40080dd3ae22788e543245eb0c28 (diff) | |
| download | ghdl-ddf587a71472a8740b044c976b8f67c537ab0c06.tar.gz ghdl-ddf587a71472a8740b044c976b8f67c537ab0c06.tar.bz2 ghdl-ddf587a71472a8740b044c976b8f67c537ab0c06.zip | |
synth: elaborate case generate statements
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 8ac6c65cf..eca3ac783 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -852,7 +852,8 @@ package body Simul.Vhdl_Elab is Gather_Connections_Instantiation_Statement (Inst, Stmt, Sub_Inst); end; - when Iir_Kind_If_Generate_Statement => + when Iir_Kind_If_Generate_Statement + | Iir_Kind_Case_Generate_Statement => declare Sub : constant Synth_Instance_Acc := Get_Sub_Instance (Inst, Stmt); |