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authorTristan Gingold <tgingold@free.fr>2017-11-06 20:45:56 +0100
committerTristan Gingold <tgingold@free.fr>2017-11-06 20:45:56 +0100
commitc988ed8c1d6bfa36c85b27771f26a9e8f0bbeec0 (patch)
tree9e9d8dd973a823a48f751abcc87b991cf71d6c50 /src/std_names.adb
parent1984d2adb083153f03eb7775d956445772ca484f (diff)
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Preliminary support for tool directives.
Diffstat (limited to 'src/std_names.adb')
-rw-r--r--src/std_names.adb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/std_names.adb b/src/std_names.adb
index 4e2f05f04..0fd7abf89 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -503,6 +503,11 @@ package body Std_Names is
Def ("include", Name_Include);
Def ("timescale", Name_Timescale);
Def ("undef", Name_Undef);
+ Def ("protect", Name_Protect);
+ Def ("begin_protected", Name_Begin_Protected);
+ Def ("end_protected", Name_End_Protected);
+ Def ("key_block", Name_Key_Block);
+ Def ("data_block", Name_Data_Block);
-- Verilog system tasks
Def ("display", Name_Display);