diff options
| author | Tristan Gingold <tgingold@free.fr> | 2021-01-25 18:18:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-01-25 18:19:10 +0100 |
| commit | 6b81ec185f16791362ca770f391578c2a8b828f0 (patch) | |
| tree | 18aa0ed76886f1efc84fbb2d97358f29d4787617 /src/std_names.ads | |
| parent | ccc1c045a19345bc970a7ababb8ee0a260bd6194 (diff) | |
| download | ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.tar.gz ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.tar.bz2 ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.zip | |
std_names: add gclk. For #1610
Regenerate python files.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index 36fdbf249..2a7fc8dc0 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -767,7 +767,8 @@ package Std_Names is Name_Allseq : constant Name_Id := Name_First_Synthesis + 001; Name_Anyconst : constant Name_Id := Name_First_Synthesis + 002; Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; - Name_Last_Synthesis : constant Name_Id := Name_Anyseq; + Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; + Name_Last_Synthesis : constant Name_Id := Name_Gclk; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; |