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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-27 06:57:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-27 06:57:51 +0200 |
| commit | 8654319ba2be19b5a17898a25e9fb562080af284 (patch) | |
| tree | db5b1d9dcbe2edb373bc99d22819d91d83b4ba43 /src/std_names.ads | |
| parent | df6bad81d527e42c1201244e812ab238f510d7d7 (diff) | |
| download | ghdl-8654319ba2be19b5a17898a25e9fb562080af284.tar.gz ghdl-8654319ba2be19b5a17898a25e9fb562080af284.tar.bz2 ghdl-8654319ba2be19b5a17898a25e9fb562080af284.zip | |
std_names: add name keep.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index 45558cb48..4022a7493 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -770,7 +770,8 @@ package Std_Names is Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; Name_Loc : constant Name_Id := Name_First_Synthesis + 005; - Name_Last_Synthesis : constant Name_Id := Name_Loc; + Name_Keep : constant Name_Id := Name_First_Synthesis + 006; + Name_Last_Synthesis : constant Name_Id := Name_Keep; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; |