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author | Tristan Gingold <tgingold@free.fr> | 2020-02-10 18:21:38 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-10 18:21:38 +0100 |
commit | 7957698f300c2ad7ee33c4d43ad80ba3ecfe8253 (patch) | |
tree | 04dbd02f0bc2f44b4dca21d99ba57ca1e505b17f /src/synth/netlists-cleanup.adb | |
parent | 2263b763e2dbd7ca624e66d15885ac1a664f886c (diff) | |
download | ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.tar.gz ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.tar.bz2 ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.zip |
synth: remove remaining clock edge gates after memories.
Diffstat (limited to 'src/synth/netlists-cleanup.adb')
-rw-r--r-- | src/synth/netlists-cleanup.adb | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb index bb963633a..deec7186b 100644 --- a/src/synth/netlists-cleanup.adb +++ b/src/synth/netlists-cleanup.adb @@ -202,6 +202,30 @@ package body Netlists.Cleanup is Insert_Mark_And_Sweep (Inspect, Get_Net_Parent (N)); end if; end loop; + + case Get_Id (Inst) is + when Id_Mem_Rd + | Id_Mem_Rd_Sync => + -- When a memory read port is found, mark the whole + -- memory. + -- FIXME: free unused read ports. + declare + Inp : Input; + begin + loop + N := Get_Output (Inst, 0); + Inp := Get_First_Sink (N); + exit when Inp = No_Input; + pragma Assert (Get_Next_Sink (Inp) = No_Input); + Inst := Get_Input_Parent (Inp); + exit when Get_Mark_Flag (Inst); + Insert_Mark_And_Sweep (Inspect, Inst); + N := Get_Output (Inst, 0); + end loop; + end; + when others => + null; + end case; end; end loop; |