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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-27 19:28:01 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-27 19:37:33 +0200 |
| commit | a036958a9adc31011729aab02af9eec48f80bc8a (patch) | |
| tree | 2534000aaa570fde4d0359cf0c969f0d8a7a44cd /src/synth/netlists-disp_verilog.adb | |
| parent | 060840d4176d7e5b775616e8a702bd751765c753 (diff) | |
| download | ghdl-a036958a9adc31011729aab02af9eec48f80bc8a.tar.gz ghdl-a036958a9adc31011729aab02af9eec48f80bc8a.tar.bz2 ghdl-a036958a9adc31011729aab02af9eec48f80bc8a.zip | |
synth: rework #2109 - remove null wires
Diffstat (limited to 'src/synth/netlists-disp_verilog.adb')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index b2461bf2f..f28a1b536 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -1149,9 +1149,6 @@ package body Netlists.Disp_Verilog is or else (Flag_Merge_Edge and then Id in Edge_Module_Id and then not Need_Edge (Inst)) - or else (not Flag_Null_Wires - and then Get_Nbr_Outputs (Inst) = 1 - and then Get_Width (Get_Output (Inst, 0)) = 0) then -- Not displayed. null; |